Intel Xeon Processor 2.80 GHz Specification Update

12 Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update
Summary Tables of Changes
D52 x No Fix Writing the local vector table (LVT) when an interrupt is pending may cause an unexpected interrupt
D53 x No Fix The processor may issue multiple code fetches to the same cache line for systems with slow memory
D54 x No Fix IRET under certain conditions may cause an unexpected Alignment Check Exception
D55 x No Fix Using 2M/4M pages when A20M# is asserted may result in incorrect address translations.
D56 x No Fix
Writing shared unaligned data that crosses a cache line without proper semaphores or barriers may
expose a memory ordering issue.
D57 x No Fix Processor may hang during entry into No-Fill Mode or No-Eviction Mode.
D58 x No Fix FPU Operand pointer may not be cleared following FINIT/FNINIT.
D59 X No Fix
The IA32_MC0_STATUS/IA32_MC1_STATUS/ IA32_MC4_STATUS Overflow Bit is not set when
multiple un-correctable machine check errors occur at the same time.
D60 X No Fix Debug Status Register (DR6) Breakpoint Condition Detected Flags may be set incorrectly.
Specification Changes
No. SPECIFICATION CHANGES
None for this revision of this specification update.
Specification Clarifications
No. SPECIFICATION CLARIFICATIONS
None for this revision of this specification update.
Documentation Changes
No. DOCUMENTATION CHANGES
None for this revision of this specification update.
Errata (Sheet 3 of 3)
No. A0 Plans Description