64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update 29
Errata
U47 The Execute Disable Bit fault may be reported before other types of page
fault when both occur
Problem: If the Execute Disable Bit is enabled and both the Execute Disable Bit fault and page faults occur,
the Execute Disable Bit fault will be reported prior to other types of page fault being reported.
Implication: No impact to properly written code since both types of faults will be generated but in the opposite
order.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U48 Writes to IA32_MISC_ENABLE may not update flags for both logical
processors
Problem: Due On processors supporting HT Technology with Execute Disable Bit feature, writes to
IA32_MISC_ENABLE may only update IA32_EFER.NXE for the current logical processor.
Implication: Due to this erratum, the non-current logical processor may not update its IA32_EFER.NXE bit.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U49 Execute Disable Bit set with CR4.PAE may cause livelock
Problem: If the Execute Disable bit of IA32_MISC_Enable is set along with the PAE bit of CR4
(IA32_EFER.NXE & CR4.PAE), the processor may livelock.
Implication: When this erratum occurs, the processor may livelock resulting in a system hang or operating
system failure.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U50 Checking of page table base address may not match address bit width
supported by the platform
Problem: If the page table base address included in the page map level-4 table, page-directory pointer table,
page-directory table or page table exceeds the physical address range supported by the platform
(e.g. 36 bits) and it is less than the implemented address range (e.g. 40 bits), the processor does not
check to see if the address is invalid.
Implication: If software sets such an invalid physical address in the listed tables, the processor does not generate
a page fault (#PF) upon accessing that virtual address and the access results in an incorrect read or
write. If BIOS provides only valid physical address ranges to the operating system, this erratum
will not occur.
Workaround: Ensure that BIOS provides only valid physical address ranges to the operating system.
Status: For the steppings affected, see the Summary Table of Changes.
U51 A32_MCi_STATUS MSR may improperly indicate that additional MCA
information may have been captured
Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the
IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR
and IA32_MCi_MISC MSRs were not properly captured.
Implication: If this erratum occurs, the MCA information captured in the IA32_MCi_ADDR and
IA32_MCi_MISC registers may not correspond to the reported machine-check error, even though
the ADDRV and MISCV are asserted.
Workaround: None identified.