Intel Xeon Processor Multiprocessor Platform Design Guide

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Mechanical and EMI Design Considerations
7.2.5 EMI Design Considerations
The following sections discuss design techniques that may be applied to minimize EMI emissions.
Some ideas have been incorporated into Intel-enabled designs (differential clock drivers, selective
clock gating, etc.) and some must be implemented by motherboard designers (trace routing,
clocking schemes, etc.).
7.2.6 Spread Spectrum Clocking (SSC)
Spread Spectrum Clocking is defined as continuously ramping (or modulating) the processor clock
frequency over a predefined range (see Figure 7-4). SSC reduces radiated emissions by spreading
the radiated energy over a wider frequency band (see Figure 7-5). Thus, instead of maintaining a
constant system frequency, SSC modulates the clock frequency along a predetermined path (or
modulating profile, Figure 7-4) with a predetermined modulation frequency. The modulation
frequency is usually selected to be larger than 30 kHz (above the audio band) while small enough
not to upset system timings (less than 0.8% of the clock frequency). SSC has been demonstrated to
effectively reduce peak radiation levels, making EMC compliance easier to achieve.
To conserve the minimum period requirement for bus timing, the SSC clock is modulated between
fnom and (1-d) fnom where fnom is the nominal frequency for a constant frequency clock. d
specifies the total amount of spreading as a relative percentage of fnom. The modulation
percentage is always a function of 1-d and not 1+d, as increasing the clock frequency above the
rated speed of the processor may cause unpredictable operation.
Figure 7-4. Spread Spectrum Modulation Profile
(1- δ
δδ
δ )fnom
time
f
nom
1/fm
System clock as a
res ul t of S S C