Intel Xeon Processor MP Specification Update

20 Intel
®
Xeon
®
Processor MP Specification Update
Errata
O5 Shutdown and IERR# may result due to a machine check exception on a
Hyper-Threading Technology enabled processor
Problem: When a Machine Check Exception (MCE) occurs due to an internal error, both logical processors
on a Hyper-Threading (HT) Technology enabled processor normally vector to the MCE handler.
However, if one of the logical processors is in the “Wait for SIPI” state, that logical processor will
not have a MCE handler and will shut down and assert IERR#.
Implication: A processor with a logical processor in the “Wait for SIPI” state will shut down when an MCE
occurs on the other thread.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O6 When in no-fill mode (CR0.CD=1) the memory type of large (PSE-4M and
PAE-2M) pages are wrongly forced to uncacheable
Problem: When the processor is operating in No-Fill Mode (CR0.CD=1), the page miss hardware incorrectly
forces the memory type of large (PSE-4M and PAE-2M) pages to UC memory type regardless of
the MTRR settings. By forcing the memory type of these pages to UC, load operations, which
should hit valid data in the L1 cache, are forced to load the data from system memory. Some
applications will lose the performance advantage associated with the caching permitted by other
memory types.
Implication: This erratum may result in some performance degradation when using no-fill mode with large
pages.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O7 Processor may hang due to speculative page walks to non-existent system
memory
Problem: A load operation issued speculatively by the processor that misses the data translation lookaside
buffer (DTLB) results in a page-walk. A branch instruction older than the load retires so that this
load operation is now in the mispredicted branch path. Due to an internal boundary condition, in
some instances the load is not cancelled before the page walk is issued.
The page miss handler (PMH) starts a speculative page-walk for the Load and issues a cacheable
load of the page directory entry (PDE). This PDE loads returns data that points to a page table entry
in UC memory. The PMH issues the PTE Load to UC space, which is issued on the system bus. No
response comes back for this load PTE operation since the address is pointing to system memory
that does not exist.
This load to non-existent system memory causes the processor to hang because other bus requests
are queued up behind this UC PTE load which never gets a response. If the load was accessing
valid system memory, the speculative page-walk would successfully complete and the processor
would continue to make forward progress.
The boundary conditions to generate this erratum are more likely to occur with HT Technology
enabled but may also occur with HT Technology disabled.
Implication: Processor may hang due to speculative page walks to non-existent system memory.
Workaround: Page directories and page tables in UC memory space must point to system memory that exists.
Status: For the steppings effected, see the Summary Table of Changes.