Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

6 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
8.2.7.4 Tri-State Buffer or 2:1 Multiplexer for HPx_SLOT [2:0] ...... 132
8.2.7.5 HPx_SID Output Signal ...................................................... 132
8.2.7.6 Pull-Ups/Pull-Downs in Dual-Slot Parallel Mode ................ 132
8.2.7.7 Hot-Plug Multiplexed Signals in Dual-Slot Parallel Mode ... 133
8.2.7.8 SMBus Address Considerations......................................... 134
8.2.7.9 Reference Schematic for Dual-Slot Parallel Mode ............. 135
8.2.8 Three or More Slot Serial Mode ....................................................... 136
8.2.8.1 Hot-Plug and Non-Hot-Plug Combinations ......................... 136
8.2.8.2 Required Additional Logic................................................... 136
8.2.8.3 Debounced Hot-Plug Switch Input...................................... 136
8.2.8.4 Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins........... 136
8.2.8.5 HPx_SLOT [2:0] ................................................................. 136
8.2.8.6 Stutter Logic for Implementing Fewer Than Six Slots ........ 136
8.2.8.7 Pull-Ups/Pull-Downs in Three or More Slot Serial Mode .... 137
8.2.8.8 Reference Schematic for Serial Mode ................................ 138
8.2.9 Intel
®
P64H2 PCI Interface PCIXCAP and M66EN Pins.................. 139
8.2.9.1 PCIXCAP Pin Requirements .............................................. 139
8.2.9.2 M66EN Pin Requirements .................................................. 139
9 I/O Controller Hub 3 (Intel
®
ICH3-S)................................................................143
9.1 IDE Interface ..................................................................................................... 143
9.1.1 Cabling ............................................................................................. 143
9.1.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100 ...................... 144
9.1.2.1 Combination Host-Side/Device-Side Cable Detection........ 144
9.1.3 IDE Connector Requirements .......................................................... 145
9.2 SPKR Pin Consideration ................................................................................... 146
9.3 PCI .................................................................................................................... 146
9.4 USB................................................................................................................... 147
9.4.1 General Routing and Placement ...................................................... 147
9.4.2 USB Routing Parameters ................................................................. 148
9.4.3 EMI Considerations .......................................................................... 148
9.4.4 USB Power Line Layout Topologies................................................. 148
9.5 Intel
®
ICH3-S SMBus/SMLink Interface ............................................................ 149
9.5.1 SMBus Design Considerations......................................................... 150
9.5.2 The Unified VCC_CORE Architecture.............................................. 150
9.5.3 High Power/Low Power Mixed Architecture ..................................... 151
9.5.4 Calculating The Physical Segment Pull-Up Resistor........................ 152
9.6 Real Time Clock (RTC) ..................................................................................... 153
9.6.1 RTC External Circuit......................................................................... 154
9.6.2 RTC External RTCRST# Circuit ....................................................... 154
9.6.3 External Capacitors .......................................................................... 155
9.6.4 RTC Layout Considerations ............................................................. 156
9.6.5 RTC External Battery Connection .................................................... 156
9.6.6 VBIAS DC Voltage and Noise Measurements ................................. 156
9.6.7 SUSCLK ........................................................................................... 157
9.6.8 RTC-Well Input Strap Requirements................................................ 157
9.7 Internal LAN Layout Guidelines ........................................................................ 158
9.7.1 LCI (LAN Connect Interface) Guidelines .......................................... 159
9.7.1.1 Bus Topology...................................................................... 159
9.7.1.2 LCI Routing Parameters ..................................................... 160
9.7.2 General LAN Routing Guidelines and Considerations ..................... 161