Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 221
High-Speed Design Concerns
However, it would unbalance the Processor 0/MCH path by a total length of 2*SignalX
PLC
since
this path does not contain propagation along the Processor 1 package. The Processor 0/MCH path
has the longest propagation in the system and presents the highest risk of mismatch between the
signals and associated strobe due to the Processor 1 package stubs. The best pad-to-pad
compensation for the Processor 0/MCH direction, excludes 2 SignalX
PLC
lengths at Processor 1.
The length matching equations are based on the PLC and SI concepts explained in the previous two
sections. The total pad-to-pad length is represented by the following equations for each of the three
possible driver/receiver paths and can be derived by adding the total lengths as illustrated in
Figure 12-15.
Equation 12-5. Processor 0/Processor 1 Length Matching
Signal X
Processor 1 Die Pad-to-Processor 0 Die Pad
= SignalX
Processor Package Length
+ SignalX
Processor PLC
+ Shortest Signal
Processor 0 to Processor 1 PCB Length
+ Signal X
SI Adj
+ SignalX
Processor Package Length
Equation 12-6. Processor 1/MCH Length Matching
SignalX
Processor 1 Die Pad-to-MCH Die Pad
= SignalX
Processor Package Length
+ SignalX
SI Adj
+ Shortest Signal
Processor 1 to MCH PCB Length
+ SignalX
MCH PLC
+ SignalX
MCH Package Length
Equation 12-7. Processor 0/MCH Length Matching
SignalX
Processor 0 Die Pad-to-MCH Die Pad
= SignalX
Processor Package Length
+ SignalX
Processor PLC
+ Shortest Signal
Processor 0 to Processor 1 PCB Length
+ SignalX
SI Adj
+ SignalX
SI Adj
+ Shortest Signal
Processor 1 to MCH PCB Length
+ SignalX
MCH PLC
+ SignalX
MCH Package Length
Equation 12-3 and Equation 12-4 are used to generate the various PLC and SI Adjustment Length
parameters for these equations. Extracting specific parameters from Equation 12-5, the total
motherboard length for Signal X in the Processor 0/Processor 1 path is defined in Equation 12-8.
Similarly, extracting specific parameters from Equation 12-6, the total motherboard length for
Signal X in the Processor 0/Processor 1 path is defined in Equation 12-9.
Equation 12-8. Processor 0 to Processor 1 PCB Length Definition
SignalX
Processor 0 to Processor 1 PCB Length
= SignalX
Processor PLC
+ SignalX
SI Adj
+ Shortest Signal
Processor 0 to Processor 1 PCB Length
Equation 12-9. Processor 1 to MCH PCB Length Definition
SignalX
Processor 1 to MCH PCB Length
= SignalX
MCH PLC
+ SignalX
SI Adj
+ Shortest Signal
Processor 1 to MCH PCB Length