Intel Xeon Processor Specification Update

38 Intel
®
Xeon
®
Processor Specification Update
Errata
Status: For the steppings affected, see the Summary Table of Changes.
P35 Livelock may occur when bus parking is disabled
Problem: A livelock may occur when processor bus parking is disabled, and when (1) the processor is the
symmetric owner of the bus with one internal request pending, and (2) the processor observes the
assertion of BPRI#, BNR# or a full IOQ. In this scenario, the processor bus interface unit assumes
that the assertion of ADS# is not required, deasserts BREQ, and, as a result, relinquishes bus
ownership without issuing the pending request. If the BPRI#, BNR# or full IOQ pattern continues
coincident with the arbitration phase of the processor that still has only one outstanding internal
request, livelock may occur. Assertion of bus parking, any change to the regular pattern of BPRI#
or BNR# assertion noted above, or the arrival of a second internal transaction will release the
processor from the livelock condition
.
Implication: This erratum may result in a livelock.
Workaround: This erratum can be avoided by enabling bus parking. The deassertion of signal A15# during the
active-to- inactive edge of RESET# will enable bus parking.
Status: For the steppings affected, see the Summary Table of Changes.
P36 CR2 May be incorrect or an incorrect page-fault error code may be pushed
on to stack after execution of an LSS instruction
Problem: Under certain timing conditions, the internal load of the selector portion of the LSS instruction
may complete with potentially incorrect speculative data before the load of the offset portion of the
address completes. The incorrect data is corrected before the completion of the LSS instruction but
the value of CR2 and the error code pushed on the stack are reflective of the speculative state. Intel
has not observed this erratum with commercially available software.
Implication: When this erratum occurs, the contents of CR2 may be off by two, or an incorrect page-fault error
code may be pushed onto the stack.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
P37 Buffer on resistance may exceed specification
Problem: The datasheet specifies the resistance range for buffer on resistance (RON) for the AGTL+ buffer
as 5 to 11 ohms. Due to this erratum, RON may be as high as 12 ohms.
Implication: The RON value affects the voltage level of the signals when the buffer is driving the signal low. A
higher RON may adversely affect the system's ability to meet specifications such as VIL. As the
system design also affects margin to specification, designs may or may not have sufficient margin
to function properly with an increased RON. System designers should evaluate whether a particular
system is affected by this erratum. Designs that follow the recommendations in the Intel
®
Xeon
®
Processor and Intel
®
860 Chipset Platform Design Guide are not expected to be affected.
Workaround: No workaround is necessary for systems with margin sufficient to accept a higher R
ON
.
Status: For the steppings affected, see the Summary Table of Changes.
P38 Instruction pointer stored on stack may become invalid
Problem: The instruction pointer stored on the stack my become invalid due to an internal boundary
condition which may exist on a Hyper-Threading Technology (HT Technology) enabled
processors. The following sequence of events must occur in order to encounter this erratum:
• One logical processor executes the WRMSR instruction with incorrect data causing a general
protection fault.