Intel Xeon Processor Multiprocessor Platform Design Guide

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8.12 Generating and Distributing GTLREF[3:0] ..........................................................83
8.12.1 GTLREF [3:0] .........................................................................................84
8.13 Filter Specifications for V
CCA
, V
CCIOPLL
, and V
SSA
.............................................85
9 Methodology for Determining Topology and Routing Guidelines.......91
9.1 Timing Methodology ............................................................................................92
9.1.1 Source Synchronous ..............................................................................92
9.1.1.1 Setup Time ................................................................................93
9.1.1.2 Hold Time ..................................................................................94
9.1.2 Common Clock.......................................................................................95
9.1.2.1 Setup Margin .............................................................................96
9.1.2.2 Hold Margin ...............................................................................98
9.1.3 Data and Address Setup Time to BCLK.................................................98
9.1.4 Timing Spreadsheet ...............................................................................98
9.2 Simulation Methodology ......................................................................................99
9.2.1 Design Optimization ............................................................................... 99
9.2.2 Signal Categories and Topology Options...............................................99
9.2.3 Sensitivity Analysis.................................................................................99
9.2.4 Signal Quality Metrics...........................................................................100
9.2.4.1 Noise Margin ...........................................................................100
9.2.4.2 Ringback .................................................................................101
9.2.5 Timing Metrics ......................................................................................101
9.2.5.1 Setup Flight Time .................................................................... 101
9.2.5.2 Calculating Flight Time for Signals with Corrupt Signal
Quality .....................................................................................101
9.2.5.3 Incorporating Package Effects into the Flight Time.................103
9.2.6 Parameter Sweeps and Monte Carlo Analysis..................................... 103
9.2.6.1 Parameter Sweeps..................................................................104
9.2.6.2 Final Solution Space ............................................................... 106
10 System Theory ........................................................................................................107
10.1 AGTL+ Logic .....................................................................................................107
10.2 Inter-Symbol Interference..................................................................................107
10.3 Crosstalk ...........................................................................................................109
10.3.1 Single Line Equivalent Model (SLEM)..................................................112
10.3.2 Serpentine Traces ................................................................................113
11 Design Checklist.....................................................................................................115
11.1 Processor Family Connection Checklist............................................................115