Intel Xeon Processor Multiprocessor Platform Design Guide

31
System Bus Routing
System Bus Routing 6
Table 6-1 summarizes the layout recommendations for 4-way processor-based configurations. It
should be used for quick reference only. The following sections provide more detailed information
about the different system configurations.
Table 6-1. System Bus Routing Summary for 4-Way Processor Configurations (Sheet 1 of 2)
Parameter
4-Way: Intel
®
Xeon™ Processor MP and Intel
®
Xeon™ Processor MP
with up to 2-MB L3 Cache on the 0.13 Micron Process
Line to line spacing Greater than 3:1 edge-to-edge spacing vs. trace to reference plane height
ratio
4X Signal Group line lengths
(agent-to-agent spacing)
3.0” – 6.1” pin-to-pin. The maximum distance between one and only one
set of agents may be up to 6.9 inches, e.g., from processor 2 and
processor 3 at the “U-turn” route.
Total bus length must not exceed 20.8
Length must be added to the motherboard trace between agents to
compensate for the stub created by the processor package. See
Section 6.4.1.1 for details.
DSTBn/p[3:0]# line lengths DSTB# signals should follow the same routing rules as the Data signals.
In addition:
A 25-mil spacing should be maintained around each strobe signal (between
DSTBp# and DSTBn#, and any other signal.)
2X Signal Group line lengths Address signals should follow the same routing rules as the Data signals.
ADSTB[1:0]# line lengths ADSTB# signals should follow the same routing rules at the DSTB# signals.
Common Clock signal line
lengths
Common Clock signals should follow the same routing rules at the Data
signals, however no length compensation is necessary.
Topology Daisy chain with chipset at one end of the system bus and Processor 0 at the
other (U-turn may exist between Processor 2 and Processor 3.)
End processor (Processor 0) must have on-die termination enabled.
Routing Requirements No motherboard contribution to stub length of middle processors (35 mil max
trace via to pad.)
Strobes and associated signals must be routed on same layer for entire
length of bus.