Intel Xeon Processor LV and ULV Specification Update

Errata

Specification Update 33

Workaround: Operating systems should not allow A20M# to be enabled if the masking of address

bit 20 could be applied to an address that references a large page. A20M# is normally

only used with the first megabyte of memory.

Status: For the steppings affected, see the Summary Tables of Changes.

AF48. Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and

IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Architectural

Performance Monitoring) Specification

Problem: According to the Architectural Performance Monitoring specification the two PerfMon

counters can be disabled/enabled through the corresponding Counter Enable bit [22]

of IA32_CR_PerfEvtSel0/1.

Due to this erratum the following occurs:

1. bit [22] of IA32_CR_PerfEvtSel0 enables/disables both counters

2. bit [22] of IA32_CR_PerfEvtSel1 doesn't function

Implication: ImplicatiSoftware cannot enable/disable only one of the two PerfMon counters through

the corresponding Counter Enable bit [22] of IA32_CR_PerfEvtSel0/1.

Workaround: Software should enable/disable both PerfMon counters together through Counter

Enable bit [22] of IA32_CR_PerfEvtSel0 only. Alternatively, Software can effectively

disable any one of the counters by clearing both Krnl and App bits [17:16] in the

corresponding IA32_CR_PerfEvtSel0/1.

Status: For the steppings affected, see the Summary Tables of Changes.

AF49. Prior Premature Execution of a Load Operation to Exception Handler

Invocation

Problem: If any of the below circumstances occur it is possible that the load portion of the

instruction will have executed before the exception handler is entered.

• If an instruction that performs a memory load causes a code segment limit

violation

• If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX)

instruction that performs a memory load has a floating-point exception pending.

• If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a

memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Top-of-

Stack (FP TOS) not equal to 0, or a DNA exception pending.

Implication: In normal code execution where the target of the load operation is to write back

memory there is no impact from the load being prematurely executed, or from the

restart and subsequent re-execution of that instruction by the exception handler. If

the target of the load is to uncached memory that has a system side-effect, restarting

the instruction may cause unexpected system behavior due to the repetition of the

side-effect. Particularly, while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM

Workaround: Code which performs loads from memory that has side-effects can effectively

workaround this behavior by using simple integer-based load instructions when

accessing side-effect memory and by ensuring that all code is written such that a code

segment limit violation cannot occur as a part of reading from side-effect memory.