64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

14 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update
Summary Table of Changes
U59 X No Fix An REP MOVS or an REP STOS instruction with RCX >= 2^32 may fail to execute to completion
or may write to incorrect memory locations on processors supporting Intel
®
Extended Memory 64
Technology (Intel
®
EM64T)
U60 X No Fix An REP LODSB or an REP LODSD or an REP LODSQ instruction with RCX >= 2^32 may cause a
system hang on processors supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
U61 X No Fix The IA32_MC0_STATUS/IA32_MC1_STATUS/ IA32_MC4_STATUS Overflow Bit is not set when
multiple un-correctable machine check errors occur at the same time.
U62 X No Fix Disabled correctable machine check errors may be logged as disabled uncorrectable errors
U63 X No Fix Machine check registers may contain incorrect information if a correctable error is followed by a
un-correctable error
U64 X No Fix Deferred Phase Support (DPS#) and Deferred Enable (DEN#) are asserted when Branch Trace
Messages (BTMs) are issued
U65 X No Fix A data Access which spans both the canonical and the non-canonical address space may hang
the system
U66 X No Fix A 64-bit value of Linear Instruction Pointer (LIP) may be reported incorrectly in the Branch Trace
Store (BTS) Memory or in the Precise Event Based Sampling (PEBS) memory record
U67 X Plan Fix It is possible that two specific invalid opcodes may cause unexpected memory accesses
U68 X No Fix At core-to-bus ratios of 16:1 and above Defer Reply transactions with non-zero REQb values may
cause a Front Side Bus stall
U69 X No Fix The processor may issue Front Side Bus transactions up to 6 clocks after RESET# is asserted
U70 X No Fix Front Side Bus machine checks may be reported as a result of on-going transactions during warm
reset
U71 X No Fix Writing the Local Vector Table (LVT) when an interrupt is pending may cause an unexpected
interrupt
U72 X No Fix The processor may issue multiple code fetches to the same cache line for systems with slow
memory
U73 X No Fix Starting BCLK prior to VCC being stable may cause start up problems with PLL
U74 X No Fix IRET under certain conditions may cause an unexpected Alignment Check Exception
U75 X No Fix Using 2M/4M pages when A20M# is asserted may result in incorrect address translations.
U76 X No Fix Writing shared unaligned data that crosses a cache line without proper semaphores or barriers
may expose a memory ordering issue.
U77 X No Fix Processor may hang during entry into No-Fill Mode or No-Eviction Mode.
U78 X No Fix FPU operand pointer may not be cleared following FINIT/FNINIT.
U79 X No Fix L2 cache ECC machine check errors may be erroneously reported after an asynchronous
RESET# assertion.
U80 X No Fix Debug Status Register (DR6) Breakpoint Condition Detected Flags may be set incorrectly.
U81 X No Fix A Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E or PDPTE.
Errata (Sheet 3 of 3)
No.
C-0/
0F41h
Plans ERRATA