Intel Xeon Processor MP Specification Update

Intel
®
Xeon
®
Processor MP Specification Update 15
Summary Tables of Changes
Errata (Sheet 1 of 4)
No.
0F11h
/C0
0F22h/
A0
OF25h\/
B0
0F26h/
C0
Plans Errata
O1 XFixedUC code in same line as write back (WB) data may lead to data
corruption
O2 XXXXNo FixTransaction is not retried after BINIT#
O3 XX
XX
No Fix Invalid opcode 0FFFh requires a ModRM byte
O4 XX
XX
No Fix FSW may not be completely restored after page-fault on FRSTOR
or FLDENV instructions
O5 XX
XX
No Fix Shutdown and IERR# may result due to a machine check
exception on a Hyper-Threading Technology enabled processor
O6 XX
XX
No Fix When in no-fill mode (CR0.CD=1) the memory type of large
(PSE-4M and PAE-2M) pages are wrongly forced to uncacheable
O7 XX
XX
No Fix Processor may hang due to speculative page walks to
non-existent system memory
O8 XFixedWriting a performance counter may result in an incorrect counter
value
O9 XFixedPerformance counter may contain incorrect value after being
stopped
O10 XX
XX
No Fix Memory type of the load lock different from its corresponding store
unlock
O11 XX
XX
No Fix Machine check architecture error reporting and recovery may not
work as expected
O12 XX
XX
No Fix Debug mechanisms may not function as expected
O13 XFixedProcessor may timeout waiting for a device to respond after 0.67
seconds
O14 XX
XX
No Fix Cascading of performance counters does not work correctly when
forced overflow is enabled
O15 XX
XX
No Fix EMON event counting of x87 loads may not work as expected
O16 XFixedSimultaneous code breakpoint and uncorrectable error results in a
processor hang
O17 XFixedSoftware controlled clock modulation using a 12.5% or 25% duty
cycle may cause the processor to hang
O18 XFixedProcessor samples bus frequency power-on configuration pins at
the assertion of PWRGOOD
O19 XFixedPAT index MSB may be calculated incorrectly
O20 XX
XX
No Fix System bus interrupt messages without data which receive a
hardfailure response may hang the processor
O21 XX
XX
No Fix Bus invalidate line requests that return unexpected data may
result in L1 cache corruption
O22 XX
XX
No Fix The processor signals page-fault exception (#PF) instead of
alignment check exception (#AC) on an unlocked CMPXCHG8B
instruction
O23 XX
XX
No Fix Incorrect data may be returned when page tables are located in
write combining (WC) memory
O24 XFixedMultiprocessor boot protocol may not complete with an IOQ depth
of one
O25 XX
XX
No Fix Write combining (WC) load may result in an unintended address
on system bus