64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update

30 64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update
Errata
J42. FXRSTOR may not restore non-canonical effective addresses on
processors with Intel*sup
Problem: Intel EM64T enabled.
Problem: If an x87 data instruction has been executed with a non-canonical effective address, FXSAVE may
store that non-canonical FP Data Pointer (FDP) value into the save image. An FXRSTOR
instruction executed with 64-bit operand size may signal a General Protection Fault (#GP) if the
FDP or FP Instruction Pointer (FIP) is in non-canonical form.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter an unintended #GP fault.
Workaround: Software should avoid using non-canonical effective addressing in EM64T enabled processors.
BIOS can contain a workaround for this erratum removing the unintended #GP fault on
FXRSTOR.
Status: For the steppings affected, see the Summary Table of Changes.
J43. A push of ESP that faults may zero the upper 32 bits of RSP
Problem: In the event that a push ESP instruction, that faults, is executed in compatibility mode, the
processor will incorrectly zero upper 32-bits of RSP.
Implication: A Push of ESP in compatibility mode will zero the upper 32-bits of RSP. Due to this erratum, this
instruction fault may change the contents of RSP. This erratum has not been observed in
commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J44. Enhanced halt state (C1E) voltage transition may affect a system’s power
management in a Hyper-Threading Technology enabled processor
Problem: In an HT Technology enabled system, the second logical Processor may fail to wake up from
“Wait-for-SIPI” state during a C1E voltage transition.
Implication: This erratum may affect a system’s entry into the power management mode offered by the C1E
event for HT Technology enabled platforms.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J45. Enhanced halt state (C1E) may not be entered in a Hyper-Threading
Technology enabled processor
Problem: If the IA32_MISC_ENABLE MSR (0x1A0) C1E enable bit is not set prior to an INIT event on an
HT Technology enabled system, the processor will not enter C1E until the next SIPI wakeup event
for the second logical processor.
Implication: Due to this erratum, the processor will not enter C1E state.
Workaround: If C1E is supported in the system, the IA32_MISC_ENABLE MSR should be enabled prior to
issuing the first SIPI to the second logical processor.
Status: For the steppings affected, see the Summary Table of Changes.
J46. When the execute disable bit function is enabled a page fault in a
mispredicted branch may result in a page fault exception
Problem: If a page fault in a mispredicted branch occurs in the ITLB, it should not be reported by the
processor. However, if the execute disable bit function is enabled (IA32_EFER.NXE = 1) and there
is a page fault in a mispredicted branch in the ITLB, a page fault exception may occur.