Intel Xeon Processor LV and ULV Specification Update

Errata
Specification Update 37
since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers
of debug tools should be aware of the potential incorrect debug event signaling
created by this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AF59. Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Lead to Partial Memory Update
Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state
restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit
while the processor is operating in 16-bit mode or if a memory address exceeds the
4GB limit while the processor is operating in 32-bit mode.
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected
but the memory state may be only partially saved or restored.
Workaround: Software should avoid memory accesses that wrap around the respective 16-bit and
32-bit mode memory limits
Status: For the steppings affected, see the Summary Tables of Changes.
AF60. Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update
the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their
data invalid. The corresponding data if sent out as a BTM on the system bus will also
be incorrect.
Note: This issue would only occur when one of the three above mentioned debug
support facilities are used.
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be
used.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF61. Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
Problem: Memory type aliasing occurs when a single physical page is mapped to two or more
different linear addresses, each with different memory type. Memory type aliasing
with the memory types WB and WT may cause the processor to perform incorrect
operations leading to unpredictable behavior.
Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable
behavior. Intel chipset-based platforms are not affected by this erratum.
Workaround: None identified. Intel does not support the use of WB and WT page memory type
aliasing.
Status: For the steppings affected, see the Summary Tables of Changes.