Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

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Intel

®

Xeon™ Processor and Intel

®

E7500/E7501 Chipset Compatible Platform Design Guide 47

Platform Clock Routing Guidelines

Figure 4-1. System Clocking Diagram

D

I

M

M

D

I

M

M

D

I

M

M

D

I

M

M

D

I

M

M

D

I

M

M

D

I

M

M

D

I

M

M

CLK66

CLK33_ICH3-S

Super I/O

FWH

P

C

I

P

C

I

P

C

I

P

C

I

32 bit

33MHz

CPU / CPU# (4)

PCIF (3)

PCI (7)

66BUF (5)

CLK33 x7

CLK33 (x4)

DIMMclk (x4 pr.)

DDR

Channel A

MCH

ITP

Processor

Processor

Intel

®

ICH-S

CK408B

Intel

®

P64H2

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

PCIclk

x7

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

P

C

I

Host_CLK

DDR

Channel B

DIMMclk (x4 pr.)

PCIclk

x7

PCIclk

x7

PCIclk

x7

PCIclk

x7

PCIclk

x7

USBCLK

USB-48MHz (1)

CLK14

REF0 (1)

CLK66

x3

BMC

P64H2 P64H2