Dual-Core Intel Xeon Processor 2.80 GHz Specification Update

Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update 21
Errata
Implication: When this erratum occurs, an incorrect instruction stream may be executed resulting in
unpredictable software behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
D25. Using STPCLK# and executing code from very slow memory could lead to a
system hang
Problem: The system may hang when the following conditions are met:
1. Periodic STPCLK# mechanism is enabled via the chipset
2. Hyper-Threading Technology is enabled
3. One logical processor is waiting for an event (i.e. hardware interrupt)
4. The other logical processor executes code from very slow memory such that every code fetch
is deferred long enough for the STPCLK# to be re-asserted.
Implication: If this erratum occurs, the processor will go into and out of the sleep state without making forward
progress, since the logical processor will not be able to service any pending event. This erratum has
not been observed in any commercial platform running commercial software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D26. Processor provides a 4-byte store unlock after an 8-Byte load lock
Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the
Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte
load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte
store unlock occurs. Correct data information is provided since only the lower bytes change,
however external logic monitoring the data transfer may be expecting an 8 byte load lock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D27. Data breakpoints on the high half of a floating point line split may not be
captured
Problem: When a floating point load which splits a 64-byte cache line gets a floating point stack fault, and a
data breakpoint register maps to the high line of the floating point load, internal boundary
conditions exist that may prevent the data breakpoint from being captured.
Implication: When this erratum occurs, a data breakpoint will not be captured.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D28. Machine Check exceptions may not update last-exception record MSRs
(LERs)
Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check Exceptions
occur.
Implication: When this erratum occurs, the LER may not contain information relating to the machine check
exception. They will contain information relating to the exception prior to the machine check
exception.
Workaround: None identified.