64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
32 Order Number: 302402-024
Workaround:BIOS should initialize the second thread of the processor supporting HT
Technology prior to STPCLK# assertion.
Status: For the steppings affected, see the Summary Table of Changes.
S29 Incorrect duty cycle is chosen when on-demand clock
modulation is enabled in a processor supporting Hyper-
Threading Technology
Problem: When a processor supporting HT Technology enables on-demand clock
modulation on both logical processors, the processor is expected to select the
lowest duty cycle of the two potentially different values. When one logical
processor enters the AUTOHALT state, the duty cycle implemented should be
unaffected by the halted logical processor. Due to this erratum, the duty cycle
is incorrectly chosen to be the higher duty cycle of both logical processors.
Implication: Due to this erratum, higher duty cycle may be chosen when the on-demand
clock modulation is enabled on both logical processors.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S30 Memory aliasing of pages as uncacheable memory type and
write back (WB) may hang the system
Problem: When a page is being accessed as either UC or write combining (WC) and write
back (WB), under certain bus and memory timing conditions, the system may
loop in a continual sequence of UC fetch, implicit write back, and RFO retries
Implication: This erratum has not been observed in any commercially available operating
system or application. The aliasing of memory regions, a condition necessary
for this erratum to occur, is documented as being unsupported in the IA-32
Intel
®
Architecture Software Developer’s Manual, Volume 3, Section 10.12.4,
Programming the PAT. However, if this erratum occurs the system may hang
Workaround:The pages should not be mapped as either UC or WC and WB at the same
time.
Status: For the steppings affected, see the Summary Table of Changes.
S31 Using STPCLK# and executing code from very slow memory
could lead to a system hang
Problem: The system may hang when the following conditions are met:
1.Periodic STPCLK# mechanism is enabled via the chipset.
2.HT Technology is enabled.
3.One logical processor is waiting for an event (i.e. hardware interrupt).
4.The other logical processor executes code from very slow memory such that
every code fetch is deferred long enough for the STPCLK# to be reasserted.
Implication: If this erratum occurs, the processor will go into and out of the sleep state
without making forward progress, since the logical processor will not be able
to service any pending event. This erratum has not been observed in any
commercial platform running commercial software.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.