64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
20 Order Number: 302402-024
S88 XXXXXNo Fix
The processor may issue multiple code fetches to the
same cache line for systems with slow memory
S89 X
Plan
Fix
CPUID feature flag reports LAHF/SAHF as unavailable,
however the execution of LAHF/SAHF may not result
in an Invalid Opcode exception
S90 XXXXXNo Fix
IRET under certain conditions may cause an
unexpected Alignment Check Exception
S91 X Fixed
Upper 32 bits of ‘From’ address reported through LBR
or LER MSRs, BTMs or BTSs may be incorrect
S92 XXXXXNoFix
EXTEST/CLAMP may cause incorrect values to be
driven on processor pins
S93 XXXXXNo Fix
The IA32_MC0_STATUS/ IA32_MC1_STATUS Overflow
Bit is not set when multiple un-correctable machine
check errors occur at the same time.
S94 XXXXXNo Fix
Debug Status Register (DR6) Breakpoint Condition
Detected Flags May be Set Incorrectly
S95 XXXXXNo Fix
L2 Cache ECC Machine Check Errors May be
erroneously Reported after an Asynchronous RESET#
Assertion
3.2 Errata (Sheet 6 of 6)
No.
D-0/
0F34
h
E-0/
0F41
h
G-1/
0F49
h
N-0/
0F43
h
R-0/
0F4A
h
Plans Errata