64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

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64-bit Intel

Xeon

Processor MP with up to 8 MB L3 Cache Specification Update 13

Summary Table of Changes

U31 X No Fix Machine check exceptions may not update Last-Exception Record MSRs (LERs)

U32 X No Fix MOV CR3 performs incorrect reserved bit checking when in PAE paging

U33 X No Fix Stores to page tables may not be visible to page walks for subsequent loads without serializing or

invalidating the page table entry

U34 X No Fix Execution of IRET or INTn instructions may cause unexpected system behavior

U35 X No Fix Recursive page walks may cause a system hang

U36 X No Fix VERR/VERW instructions may cause #GP fault when descriptor is in non-canonical space

U37 X No Fix The base of a null segment may be non-zero on a processor supporting Intel

Extended Memory

64 Technology (Intel

EM64T)

U38 X No Fix Upper 32 bits of FS/GS with null base may not get cleared in Virtual-8086 Mode on processors

with Intel

Extended Memory 64 Technology (Intel

EM64T) Enabled

U39 X No Fix Processor may fault when the upper 8 bytes of segment selector is loaded from a far jump through

a call gate via the Local Descriptor Table

U40 X No Fix Loading a stack segment with a selector that references a non-canonical address can lead to a

#SS fault on a processor supporting Intel

Extended Memory 64 Technology (Intel

EM64T)

U41 X No Fix FXRSTOR may not restore non-canonical effective addresses on processors with Intel

Extended

Memory 64 Technology (Intel

EM64T) enabled

U42 X No Fix A push of ESP that faults may zero the upper 32-bits of RSP

U43 X No Fix Enhanced halt state (C1E) voltage transition may affect a system's power management in a HT

Technology enabled processor

U44 X No Fix Enhanced halt state (C1E) may not be entered in a HT Technology enabled processor

U45 X No Fix When the Execute Disable Bit function is enabled a page fault in a mispredicted branch may result

in a page fault exception

U46 X No Fix Execute Disable Bit set with AD assist may cause livelock

U47 X No Fix The Execute Disable Bit fault may be reported before other types of page fault when both occur

U48 X No Fix Writes to IA32_MISC_ENABLE may not update flags for both logical processors

U49 X No Fix Execute Disable Bit set with CR4.PAE may cause livelock

U50 X No Fix Checking of page table base address may not match address bit width supported by the platform

U51 X No Fix A32_MCi_STATUS MSR may improperly indicate that additional MCA information may have been

captured

U52 X No Fix With Trap Flag (TF) asserted, FP instruction that triggers unmasked FP Exception may tank single

step trap before retirement of instruction

U53 X No Fix PDE/PTE loads and continuous locked updates to the same cache line may cause system livelock

U54 X No Fix Branch Trace Store (BTS) and Precise Event-Based Sampling (PEBS) may update memory

outside the BTS/PEBS buffer

U55 X No Fix The base of an Local Descriptor Table (LDT) register may be non-zero on a processor supporting

Intel

Extended Memory 64 Technology (Intel

EM64T)

U56 X No Fix L-bit of the CS and LMA bit of the IA32_EFER register may have an erroneous value for one

instruction following a mode transition in a Hyper-Threading enabled processor supporting Intel

Extended Memory 64 Technology (Intel

EM64T)

U57 X No Fix Control Register 2 (CR2) can be updated during a REP MOVS/STOS instruction with fast strings

enabled

U58 X No Fix REP STOS/MOVS instructions with RCX >= 2^32 may cause a system hang

Errata (Sheet 2 of 3)

No.

C-0/

0F41h

Plans ERRATA