Intel Xeon Processor Multiprocessor Platform Design Guide

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Processor Power Distribution Guidelines
“V
CC
” in this 000, refers to the appropriate processor core V
CC
, cache supply voltage and Assisted
Gunning Transceiver Logic + (AGTL+) supply voltage. With Intel Xeon processors MP and Intel
Xeon processor MP with up to 2-MB L3 cache on the 0.13 micron process, the core and cache are
on the same silicon and are powered from the same power plane unlike Pentium II Xeon and
Pentium III Xeon processors, which required different power planes.
“VRM 9.1” refers to the Voltage Regulator Module for the processor. It is a DC-DC converter
module that supplies the required voltage and current to a single processor.
8.3 Power Delivery Overview
Power distribution is generally thought of as supplying power to the components that require it.
Most digital designers typically assume that an ideal supply will be provided. The printed circuit
board (PCB) designers attempt to create this ideal supply with two power planes in the PCB or by
using large width traces to distribute power. High-frequency noise created when logic gates switch
is typically controlled with high-frequency ceramic capacitors, which are recharged from lower
frequency bulk capacitors. Various rule of thumb methods exist for determining the amount of each
type of capacitance that is required. For Intel Xeon processor MP and Intel Xeon processor MP
with up to 2-MB L3 cache on the 0.13 micron process-based designs, the system designer needs to
design beyond the rule of thumb and architect a power distribution system that meets appropriate
processor specifications.
Intel Xeon processor MP and Intel Xeon processor MP with up to 2-MB L3 cache on the 0.13
micron process-based systems have the capability to use four or more processors. The processor
core and all of the caches are operating at the same voltage level, i.e., V
CC
. On-die termination is
used to pull the AGTL+ bus up to V
CC
to control reflections on the transmission line. The data bus
must route over a uniform power plane because of signal quality constraints. Consequently in a
multiprocessor system design a single power plane should be used for power delivery to all
processors. Hence, the mixing of processors operating at different voltages is not supported and
will not be validated by Intel.
8.4 Processor Power Delivery Ingredients
Discussion of processor power delivery may be broken down into seven ingredients:
1. System Design.
2. Processor Load
3. Voltage Regulator
4. Power Planes
5. Decoupling Capacitors
6. Component Placement and Modeling
7. Validation Testing