Intel Xeon Processor MP Specification Update

Intel
®
Xeon
®
Processor MP Specification Update 33
Errata
processor with HT Technology enabled, the processor should return 50h (64 entries). Due to this
erratum, the CPUID instruction always returns 50h (64 entries).
Implication: Software may incorrectly report the number of ITLB entries. Operation of the processor is not
affected.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O46 A write to APIC task priority register (TPR) that lowers priority may seem to
have not occurred
Problem: In respect to the retirement of instructions, stores to the UC memory-based APIC register space are
handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g.
CLI, is executed soon after an UC write to the task priority register (TPR) that lowers the APIC
priority, the interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR, but higher than the
final TPR, to not be serviced until the interrupt flag is finally cleared, i.e. by STI instruction.
Interrupts will remain pending and are not lost.
Implication: This condition may allow interrupts to be accepted by the processor but may delay their service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read after the APIC register
write. This will force the store to the APIC register before any subsequent instructions are
executed. No commercial operating system is known to be impacted by this erratum.
Status: For the steppings effected, see the Summary Table of Changes.
O47 Processor does not respond to break requests from ITP
Problem: On power-up and low-power state transitions, the processor's TAP circuitry may remain in the
tap-logic-reset (TLR) state.
Implication: The ITP is unable to cause a break on reset in the processor, which may prevent the loading of
processor and chipset registers, or affect the ability to debug from cold boot and low power
transitions.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O48 Erroneous BIST result found in EAX register after reset
Problem: The processor may show an erroneous built-in self test (BIST) result in the EAX register bit 0 after
reset.
Implication: When this erratum occurs, an erroneous BIST failure will be reported in the EAX register bit 0,
however this failure can be ignored since it is not accurate.
Workaround: It is possible for BIOS to workaround this issue by masking off bit 0 in the EAX register where
BIST results are written.
Status: For the steppings effected, see the Summary Table of Changes.
O49 False data strobe glitch machine check error may occur when the machine
check handler is enabled
Problem: When the machine check handler is enabled, a false data strobe glitch error may occur and be
logged into the MC0_Status register. In this case the MC0_STATUS register will contain
0xA20000001040080F. Bit 22 being set indicates that a strobe glitch error has occurred.
Implication: Data strobe glitch machine check error may occur when the machine check handler is enabled even
though no actual data strobe glitch has occurred.