Intel Xeon Processor MP Specification Update

28 Intel
®
Xeon
®
Processor MP Specification Update
Errata
O26 Processor issues inconsistent transaction size attributes for locked
operations
Problem: When the processor is in the page address extension (PAE) mode and detects the need to set the
Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte
load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte
store unlock occurs. Correct data is provided since only the lower bytes change, however external
logic monitoring the data transfer may be expecting an 8-byte store unlock.
Implication: No known commercially available chipset are affected by this erratum.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O27 Multiple accesses to the same S-state L2 cache line and ECC error
combination may result in loss of cache coherence
Problem: When a RFO cycle has a 64 bit address match with an outstanding read hit on a line in the L2 cache
which is in the S-state AND that line contains an ECC error, the processor should recycle the RFO
until the ECC error is handled. Due to this erratum, the processor does not recycle the RFO and
attempt to service both the RFO and the read hit at the same time.
Implication: When this erratum occurs, cache may become incoherent.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O28 IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid or stale
data following a data, address, or response parity error
Problem: If the processor experiences a data, address, or response parity error, the ADDRV and MISCV bits
of the IA32_MC0_STATUS register are set, but the IA32_MC0_ADDR and IA32_MC0_MISC
registers are not loaded with data regarding the error.
Implication: When this erratum occurs, the IA32_MC0_ADDR and IA32_MC0_MISC registers will contain
invalid or stale data.
Workaround: Ignore any information in the IA32_MC0_ADDR and IA32_MC0_MISC registers after a data,
address or response parity error.
Status: For the steppings effected, see the Summary Table of Changes.
O29 Instruction pointer stored on stack may become invalid
Problem: Due to an internal boundary condition which may exist on a HT Technology enabled Intel Xeon
processor MP, the following sequence of events must occur:
Caution: One logical processor executes the WRMSR instruction with incorrect data causing a general
protection fault.
1. Simultaneously an event that requires micro-architectural synchronization among the two
logical processors occurs on the second logical processor may cause an invalid instruction
pointer to be stored on the ring 0 stack during the transition to GP fault handler on the first
logical processor.
Implication: The instruction pointer stored on the stack may be invalid, potentially causing errors during
execution of or return from the GP fault handler.
Workaround: It is possible for BIOS to contain a workaround this issue. For HT Technology enabled processors;
insure all WRMSR instructions do not generate GP faults due to incorrect data.
Status: For the steppings effected, see the Summary Table of Changes.