Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel

Xeon™ Processor and Intel

E7500/E7501 Chipset Compatible Platform Design Guide 21

Introduction

NOTES:

1. Contact your Intel Field Representative for additional reference documentation.

1.3 System Overview

The E7500 and E7501 chipsets are Intel’s server chipsets designed for use with the Intel Xeon

processor. The architecture of the chipset provides the performance and feature-set required for

dual-processor based severs in the entry-level and mid-range, front-end and general-purpose server

market segments. A chipset component interconnect, the Hub Interface 2.0 (HI2.0), is designed

into the E7500/E7501 chipset to provide more efficient communication between chipset

components for high-speed I/O. Each HI2.0 provides 1.066 GB/s I/O peak bandwidth. The E7500/

E7501 chipset MCH has three HI2.0 connections, delivering 3.2 GB/s peak bandwidth for high-

speed I/O, which can be used for PCI/PCI-X bridges. The system bus is used to connect the

processor with the E7500/E7501 chipset.

The Intel

Xeon™ processor with 512-KB L2 cache system bus uses a 400 MHz transfer rate for

data transfers, delivering 3.2 GB/s. The E7500/E7501 chipset architecture supports a 144-bit wide,

200 MHz DDR memory interface also capable of transferring data at 3.2 GB/s. When the E7501

chipset is used with the Intel

Xeon™ processor with 533 MHz system bus and DDR266 DIMMs,

the processor uses a 533 MHz transfer rate for data transfers, delivering 4.27 GB/s.

The chipset only supports one clock ratio between the memory bus and processor bus. The MCH

will either run in DDR200/400 MHz, or in DDR266/533 MHz.

Intel

Xeon™ Processor with 512-KB L2 Cache Thermal Models