Intel Xeon Processor Multiprocessor Platform Design Guide

Introduction

Introduction 1

This design guide documents Intel's design recommendations for systems based on the Intel

Xeon™ processor MP and Intel

Xeon™ processor MP with up to 2-MB L3 Cache on the 0.13

Micron Process using non-Intel designed chipsets. In addition to providing motherboard design

recommendations such as layout and routing guidelines, this document will also address possible

system design issues such as processor power delivery, layout considerations for mechanical

pieces, EMI design impacts and system bus decoupling. Design issues such as thermal

considerations should be addressed using specific thermal documentation for the Intel Xeon

processor MP.

Carefully follow the design information, board schematics, debug recommendations, and system

checklist presented in this document. These design guidelines have been developed to ensure

maximum flexibility for board designers while reducing the risk of board-related issues. The

design information provided in this document falls into one of the two categories below.

Design Recommendations are items based on Intel's simulations and lab experience to date and are

strongly recommended, if not necessary, to meet the timing and signal quality specifications.

Design Considerations are suggestions for platform design that provide one way to meet the design

recommendations. They are based on the reference platforms designed by Intel. They should be

used as an example, but may not be applicable to your particular design.

Note: The guidelines recommended in this document are based on Intel’s experience developing Intel

Xeon processor MP based systems. The recommendations are subject to change.

1.1 Related Documentation

Reference the following documents for more information. Contact your Intel representative to

receive the latest revisions of collateral where the document number is not listed.

Table 1-1. References (Sheet 1 of 2)

Document Document Number

AP-485, Intel

Processor Identification and the CPUID Instruction 241618

IA-32 Intel Architecture Software Developer’s Manual

1. Volume 1: Basic Architecture

2. Volume 2: Instruction Set Reference

3. Volume 3: System Programming Guide (Preliminary)

245470

245471

245472

CK00 Clock Synthesizer/Driver Design Guidelines 249206

VRM 9.1 DC-DC Converter Design Guidelines 298646

ITP700 Debug Port Design Guide 249679

Intel

Xeon™ Processor MP Datasheet 290740

Intel

Xeon™ Processor MP with up to 2-MB L3 Cache on the 0.13 Micron Process

Datasheet

251931

Intel

Xeon™ Processor Thermal Design Guidelines 298348