64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
August 2009 Specification Update
Order Number: 302402-024 29
—Intel
®
Xeon™ Processor with 800 MHz System Bus
uncacheable write to the task priority register (TPR) that lowers the APIC
priority the interrupt masking operation may take effect before the actual
priority has been lowered. This may cause interrupts whose priority is lower
than the initial TPR but higher than the final TPR to not be serviced until the
interrupt flag is finally cleared (for example STI). Interrupts will remain
pended and are not lost
Implication: This condition may allow interrupts to be accepted by the processor but may
delay their service
Workaround:This can be avoided by issuing a TPR Read after a TPR Write that lowers the
TPR value. This will force the store to the APIC priority resolution logic before
any subsequent instructions are executed. No commercial operating system is
known to be impacted by this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S18 Parity error in the L1 cache may cause the processor to hang
Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it
is possible that the processor may hang while trying to evict the line.
Implication: If this erratum occurs, it may result in a system hang. Intel has not observed
this erratum with any commercially available software.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S19 Sequence of locked operations can cause two threads to receive
stale data and cause application hang
Problem: While going through a sequence of locked operations, it is possible for the two
threads to receive stale data. This is a violation of expected memory ordering
rules and causes the application to hang.
Implication: When this erratum occurs in an Hyper-Thread Technology enabled system, an
application may hang.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S20 A 16-bit address wrap resulting from a near branch (jump or
call) may cause an incorrect address to be reported to the #GP
exception handler
Problem: If a 16-bit application executes a branch instruction that causes an address
wrap to a target address outside of the code segment, the address of the
branch instruction should be provided to the general protection exception
handler. It is possible that, as a result of this erratum, that the general
protection handler may be called with the address of the branch target.
Implication: A 16-bit software environment which is affected by this erratum, will see that
the address reported by the exception handler points to the target of the
branch, rather than the address of the branch instruction.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.