Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide
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LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
+V3_3
+V5_0
+V3_3
+VSBY3_3
+V3_3
+V3_3
+
LPC47B27X
GP20/P17
VREF
AGND
GP37/A20_GATE
ACK~
ALF~
BUSY
CLKI32
CLOCKI
CTS1~
GP56/CTS2~/IRQ11
DCD1~
GP51/DCD2~/IRQ4
DIR~
GP40/DRVDEN0
GP41/DRVDEN1
DS0~
DSR1~
GP54/DSR2~/IRQ9
DTR1~
GP57/DTR2~/IRQ15
ERROR~
GP33FAN1
GP32/FAN2
GND2
GND3
GND4
HDSEL~
INDEX~
INIT~
IRRX2/GP34
IRTX2/GP35
GP36/KBDRST
KCLK
KDAT
LAD0
LAD1
LAD2
LAD3
LDRQ~
LFRAME~
LPCPD~
PCI_RESET~
MCLK
MDAT
MTR0~
PCI_CLK
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE
GPIO42/PME~
RDATA~
GP60/LED1
GP61/LED2
GP27/IO_SMI~
GP30/FAN_TACH2
GP31/FAN_TACH1
GP43/DDRC/FDC_PP
GP15/J1Y
GP16/J2X
GP17/J2Y
GP24/SYSOPT
GP22/P12
GP25/MIDI_IN
GP26/MIDI_OUT
GP10/J1B1
GP11/J1B2
GP12/J2B1
GP13/J2B2
GP14/J1X
RI1~
GP50/RI2~/IRQ3
RTS1~
GP55/RTS2~/IRQ10
RXD1
GP52/RXD2/IRQ5/IRRX
SER_IRQ
SLCT
SLCTIN~
STEP~
STROBE~
TRK0~
TXD1
GP53/TXD2/IRQ7/IRTX
VCC1
VCC2
VCC3
WDATA~
WGATE~
WRTPRT~
DSKCHG~
GND1
VTR
GP21/P16
+V3_3+V5_0
+V3_3
connector for debug
Depopulate if using LPC
Default I/O address is 2E
Super I/O
69 85
SIO_SUS_STAT_N
R642
10K
LPC_SMI_N
61
8.2K
R763
41
44
40
64
80
82
79
6
19
88
99
91
94
8
1
2
5
86
97
89
100
81
55
54
31
60
76
12
13
66
61
62
63
57
56
20
21
22
23
25
24
27
26
59
58
3
29
68
69
70
71
72
73
74
75
78
17
16
48
49
50
51
52
28
37
38
45
43
46
47
32
33
34
35
36
90
92
87
98
84
95
30
77
67
9
83
14
85
96
53
65
93
10
11
15
4
7
18
42
39
U68
LPC47B272IC
PCIRST_2_N
27,31,61,68
SIO_PME_N
61
SIO_PME_N
21
2.2UF
C1749
C1677
0.01UF
0.1UF
C1676
C1675
0.1UF
C1673
0.1UF
0.1UF
C1674
R641
4.7K
4.7K
R640
R759
4.7K
R762
8.2K
R764
0
R758
1K
0.1UF
C896
C895
0.1UF
ICH3_LAD0
ICH3_LAD3
ICH3_LAD[3:0]
62,68
ICH3_LAD2
ICH3_LAD1
SIO_LDRQ0_N
69
69SIO_LDRQ0_NICH3_LDRQ0_N
62
ICH3_RCIN_N
61
DS0_N
81
ICH3_A20GATE
61
COM_RXD170
ICH3_SUSCLK63
SMC_SYSOPT
GP31
ICH3_SERIRQ
61
SIO_CLK33
80
SIOCLKRUN
LPT_PD3
70
LPT_PD6
70
LPT_PD7
70
LPT_SLCTIN_N
70
ICH3_LFRAME_N
62,68
DSKCHG_N
81
STEP_N
81
DRVEN0
81
COM_DCD1_N70
KBDATA70
KBCLK70
MSDATA70
MSCLK70
COM_TXD170
COM_DSR1_N70
COM_RTS1_N70
COM_CTS1_N70
COM_DTR1_N70
COM_RI1_N70
MTR0_N
81
DIR_N
81
WDATA_N
81
WGATE_N
81
HDSEL_N
81
INDEX_N
81
TRK0_N
81
WRTPRT_N
81
RDATA_N
81
CLK_14MHZ_SIO
80
LPT_INIT_N
70
LPT_SLCT
70
LPT_PE
70
LPT_BUSY
70
LPT_ACK_N
70
LPT_ERROR_N
70
LPT_ALF_N
70
LPT_STROBE_N
70
LPT_PD5
70
LPT_PD4
70
LPT_PD2
70
LPT_PD1
70
LPT_PD0
70
DRVEN1
81
GP30
1.0INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD
11/18/02