ITP700 Debug Port Design Guide

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ITP700 Debug Port Design Guide 17
Figure 2. Recommended Layout Topology
Debug Port
System Bus
Agent
System
Clock
Driver
27 Ohms
FBO@(T
TCK
+T
BPM
)
BPMn@(T
T1
+T
BPM
)
BLCK@(T
T0
+T
BPM
)
BMMn@T
1
BLCK@T
0
TCK@T
TCK
NOTES:
1. All of the above routes must be simulated to ensure signal integrity. Failure to do so may result in non
functional ITP.
2. All combination timings in the above drawing are ±50 ps in routing length maximum.
The figure above defines propagation delays of various ITP signals from the driver to the receiver.
The following are definitions of individual trace segments that are included in the figure.
• T
TCK
– Propagation delay of the TCK trace from the debug port to the system bus agent TCK
pin
• T
BPM
– Propagation delay of the BPM traces from the debug port to the nearest system bus
agent.
• T
0
– Propagation delay of BCLK from the system clock driver to the processors and chipset
components
• T
1
– Propagation delay of the BPM traces from the driving system bus agent to the system bus
agent closest to the debug port.
1.4 ITP700 Flex Alternative Debug Port
There is a smaller version of the debug port available as an alternative that can be designed into
uniprocessor platforms. The ITP700 Flex is a single piece of flexible circuitry with a right-angled
standard male debug port connector on one end and the other end is plugged into a small footprint
surface mount connector that is soldered to the platform.
The following are the requirements that platforms must meet in order to be able to use the ITP700
Flex debug port.
• The target system cannot require the use of an external buffer for TCK
• BPM[5:0]# pins are not terminated correctly when the ITP700 Flex is not installed. The
platform must either not use BPM[5:0]# signals when ITP700 Flex is not plugged in or it must
be able to terminate BPM# [5:0]when ITP700 Flex is removed.