ITP700 Debug Port Design Guide

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ITP700 Debug Port Design Guide 69
8.1.2 AC Electrical Specifications
Table 38 - ITP System Signal AC Electrical Characteristics for the Intel
®
Itanium
®
2 Processor
Signal Parameter Min Max Unit Note
PWR PWR V
IL
Max to Tristate 150 µs
Rise Time 0.5 2 ns 1, 2, 3
Fall Time 0.5 2 ns 1, 2, 3
FBI
Skew -9 -6 ns 4
DBA#↓ to first TCK↑ 75 ns 5 DBA#
DBA#↑ to last TCK↓ 100 ns 6
DBR# DBR# Assertion Period 150 µs
NOTES:
1. Measured from 20% to 80% of transition.
2. Measured into a load to GND of 220 Ω and 10 pF.
3. FBI has the same period; time High, and time Low specifications as TCK.
4. With respect to same edge on TCK.
5. Measured from assertion of DBA# to 50% of first TCK transition.
6. Measured from release of DBA# to 50% of last TCK transition.
Table 39 - ITP JTAG Signal AC Electrical Characteristics for the Intel
®
Itanium
®
2 Processor
Signal Parameter Min Max Unit Note
Setup 5 ns 1
Hold 0.5 ns 1
TDO
Rise/Fall Time 15 ns 2
Rise/Fall Time 9 13 ns 2, 3
Period 58 ns 4
Time High 25 ns 5
TCK
Time Low 25 ns 5
Rise/Fall Time 7 16 ns 2, 6 TMS
Clock to Out -5 0 ns 7
Rise Time 0.5 2.0 ns 2, 8
Fall Time 0.5 2.0 ns 2, 8
TDI
Clock to Out -8 0 ns 7
TRST# Assert Time 300 ns
NOTES:
1. With respect to rising edge of FBO at the debug port using 50% of transition for both signals.
2. Measured from 20% to 80% of transition.
3. As measured into a 27 Ω and 35pF load to GND.
4. Measured from 50% of rising edge to 50% of next rising edge. This specification is valid for
asynchronous and synchronous operation.