Intel Xeon Processor Multiprocessor Platform Design Guide

4
6.4.2.9 Topology 9: SKTOCC# Signal................................................... 49
6.4.3 Debug Port Signals Routing Guidelines for 4-way Configurations......... 49
7 Mechanical and EMI Design Considerations................................................ 51
7.1 Retention Mechanism Placement and Keep-Outs .............................................. 51
7.2 Electromagnetic Interference Considerations ..................................................... 54
7.2.1 Introduction ............................................................................................ 54
7.2.2 Terminology ........................................................................................... 55
7.2.3 Brief EMI Theory .................................................................................... 55
7.2.4 EMI Regulations and Certifications ........................................................ 55
7.2.5 EMI Design Considerations.................................................................... 56
7.2.6 Spread Spectrum Clocking (SSC).......................................................... 56
7.2.7 Differential Clocking ............................................................................... 57
7.2.8 Heatsink Effects ..................................................................................... 58
7.2.9 EMI Ground Frames and Faraday Cages .............................................. 58
7.2.10 EMI Test Capabilities ............................................................................. 61
7.2.11 Summary ................................................................................................ 61
8 Processor Power Distribution Guidelines ..................................................... 63
8.1 Introduction ......................................................................................................... 63
8.2 Terms .................................................................................................................. 63
8.3 Power Delivery Overview .................................................................................... 64
8.4 Processor Power Delivery Ingredients ................................................................ 64
8.5 System Design .................................................................................................... 65
8.5.1 Multiple Voltages .................................................................................... 65
8.5.2 Voltage Sequencing ............................................................................... 65
8.5.3 Block Diagrams with Voltage Regulator Modules .................................. 65
8.6 Processor Load ................................................................................................... 66
8.6.1 Processor Voltage Tolerance ................................................................. 66
8.7 Voltage Regulator ............................................................................................... 67
8.7.1 Voltage Regulator Design ...................................................................... 67
8.7.2 Voltage Regulator System Matching...................................................... 67
8.7.2.1 Voltage Regulator Output.......................................................... 67
8.7.2.2 Voltage Regulator Input............................................................. 67
8.7.2.3 Voltage Regulator Cooling ........................................................ 67
8.7.2.4 Voltage Regulator Remote Sense Connection.......................... 68
8.7.2.5 Voltage Regulator Module ISHARE Connection ....................... 68
8.7.2.6 Voltage Regulator Module OUTEN Connection ........................ 68
8.8 Power Planes ...................................................................................................... 68
8.8.1 Layer Stack-Up ...................................................................................... 68
8.8.2 Sheet Inductance/Resistance and Emission Effects of Power Plane..... 69
8.9 Decoupling Capacitors ........................................................................................ 71
8.9.1 Decoupling Technology and Transient Response.................................. 71
8.9.2 Location of High-Frequency Decoupling ................................................ 71
8.9.3 Location of Bulk Decoupling................................................................... 72
8.9.4 Decoupling Recommendation ................................................................ 72
8.10 Component Placement and Modeling ................................................................. 73
8.10.1 Component Models ................................................................................ 73
8.10.2 Processor Socket-Package Lump Model ............................................... 73
8.10.3 Multi-Processor Component Placement and Models ............................. 77
8.11 Validation Testing................................................................................................ 83