Intel Xeon Processor Multiprocessor Platform Design Guide

108
System Theory
then the phase 2 solution space is acceptable. If timing violations do occur then steps should be
taken to minimize reflections on the bus, which will reduce the ISI. Typically, the best way to limit
reflections is to reduce impedance variations and minimize discontinuities (e.g., by shortening
stubs and connectors, matching impedance between packages and motherboard traces, etc.).
The worst-case ISI can be evaluated using the following procedure:
• Simulate the longest net on the bus using a long pseudo-random bit pattern for both the fast
and slow cases.
• Take the first transition of the ISI simulation as the baseline.
• Determine the rising and falling delays for each bus transition.
• Subtract the minimum and maximum delays from the baseline delays and find the worst-case
difference.
• Take the smallest negative and the greatest positive difference. This should be the worst case
ISI impact on timing.
Figure 10-1. Example of ISI Impact on Timing and Signal Integrity
Receiver waveforms
Single switching
ISI pattern
Driver starts switching
here
Different starting
voltage
due to ISI
V [ volts]
Time [ns]