Intel Xeon Processor 2.80 GHz Specification Update

8 Dual-Core Intel

Xeon

Processor 2.80 GHz Specification Update

Identification Information

The Dual-Core Intel

Xeon

processor 2.80 GHz can be identified by the following register

contents:

NOTES:

1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the

CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register

accessible through Boundary Scan.

2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the

CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register

accessible through Boundary Scan.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers

after the CPUID instruction is executed with a 2 in the EAX register. Please refer to the AP-485

Intel

Processor Identification and the CPUID Instruction Application Note for further

information on the CPUID instruction.

NOTES:

1. These parts are enabled for Enhanced Intel SpeedStep®Technology (EIST).

2. These parts are enabled for Enhanced Halt State (C1E).

Family

Model

1111b 0100b

Table 1. Dual-Core Intel

Xeon

Processor 2.80 GHz Identification Information

S-Spec

Core

Stepping

L2 Cache

Size (bytes)

CPUID

Core

Freq

(GHz)

Data Bus

Freq

(MHz)

Package and Revision Notes

SL8MA A0 2M x 2 0F48h 2.80 800

604-pin micro-PGA with 53.3 x 53.3

mm FC-PGA4 package Rev 01

1, 2