64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

26 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update
Errata
translation lookaside buffer (TLB) and used for memory operations. This erratum has not been
observed with any commercially available software.
Workaround: The guidelines in the IA-32 Intel® Architecture Software Developer’s Manual, Volume 3B:
System Programming Guide should be followed.
Status: For the steppings affected, see the Summary Table of Changes.
U34 Execution of IRET or INTn instructions may cause unexpected system
behavior
Problem: There is a small window of time, requiring alignment of many internal micro architectural events,
during which the speculative execution of the IRET or INTn instructions in protected or IA-32e
mode may result in unexpected software or system behavior.
Implication: This erratum may result in unexpected instruction execution, events, interrupts or a system hang
when the IRET instruction is executed. The execution of the INTn instruction may cause debug
breakpoints to be missed.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U35 Recursive page walks may cause a system hang
Problem: A page walk, accessing the same page table entry multiple times but at different levels of the page
table, which causes the page table entry to have its Access bit set, may result in a system hang.
Implication: When this erratum occurs, the system may experience a hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U36 VERR/VERW instructions may cause #GP fault when descriptor is in non-
canonical space
Problem: If a descriptor referenced by the selector specified for the VERR or VERW instructions is in Non-
canonical space, it may incorrectly cause a #GP fault on a processor supporting Intel
®
Extended
Memory 64 Technology (Intel
®
EM64T).
Implication: Operating systems or drivers that reference a selector in non-canonical space may experience an
unexpected #GP fault. Intel has not observed this erratum with any commercially available
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U37 The base of a null segment may be non-zero on a processor supporting
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: In IA-32e mode of the Intel EM64T processor, the base of a null segment may be non-zero.
Implication: Due to this erratum, Intel EM64T enabled systems may encounter unexpected behavior when
accessing memory using the null selector.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.