Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Introduction
24 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
1.3.2.1 Intel
®
E7500/E7501 Memory Controller Hub (MCH)
The MCH is a 1005-ball FC-BGA package and contains the following functionality:
• System Bus
— Supports dual processors at 100 MHz or 133 MHz (x4 transfers).
— System bus peak bandwidth of 3.2 GB/s (400 MHz) or 4.27 GB/s (533 MHz).
— Supports 36-bit system bus addressing model.
— 12 deep in-order queue, 2 deep defer queue.
• Memory Bus
— 144-bit wide, DDR200 / DDR266 memory interface with memory peak bandwidth of
3.2 GB/s or 4.27 GB/s.
— Supports x72, ECC, registered DDR200 / DDR266 DIMMs using 128-Mb, 256-Mb and
512-Mb DRAMs.
— Supports a maximum of 16 GB of memory.
— Supports Single 4-bit Error Correct, Double 4-bit Error Detect (S4EC/D4ED) using Intel
®
x4 Single Device Data Correction (x4 SDDC).
— Supports up to 32 simultaneous open pages.
• I/O
— Provides Hub Interface 1.5 connection for ICH3-S (Hub Interface_A):
- 266 MB/s point-to-point connection for ICH3-S with parity protection.
- 8-bit wide, 66 MHz base clock, 4X data transfer.
- Parallel termination mode for longer trace lengths.
- 64-bit inbound addressing, 32-bit outbound addressing.
— Provides 3 Hub Interface 2.0 Connections for P64H2 devices (Hub Interfaces_B, C and
D):
- 1.066 GB/s point-to-point connection per connection for I/O bridges with ECC
protection for up to 3.2 GB/s bandwidth when 3 devices are used.
- 16-bit wide, 66 MHz base clock, 8X data transfer.
- Parallel termination mode for longer trace lengths.
- 64-bit inbound addressing, 32-bit outbound addressing.
• Power Management
— Supports C0, C1, C2, S0, S1, and S5 power states. (Does not support C3, C4, S2, S3,
and S4).