64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
August 2009 Specification Update
Order Number: 302402-024 27
—Intel
®
Xeon™ Processor with 800 MHz System Bus
Workaround:Remove the software’s dependency on #AC having precedence over #PF.
Alternately, correct the page fault in the page fault handler and then restart
the faulting instruction.
Status: For the steppings affected, see the Summary Table of Changes.
S11 FSW may not be completely restored after page fault on
FRSTOR or FLDENV instructions
Problem: If the FPU operating environment or FPU state (operating environment and
register stack) being loaded by an FLDENV or FRSTOR instruction wraps around
a 64-Kbyte or 4-Gbyte boundary and a page fault (#PF) or segment limit fault
(#GP or #SS) occurs on the instruction near the wrap boundary, the upper
byte of the FPU status word (FSW) might not be restored. If the fault handler
does not restart program execution at the faulting instruction, stale data may
exist in the FSW.
Implication: When this erratum occurs, stale data will exist in the FSW.
Workaround:Ensure that the FPU operating environment and FPU state do not cross 64-
Kbyte or 4-Gbyte boundaries. Alternately, ensure that the page fault handler
restarts program execution at the faulting instruction after correcting the
paging problem.
Status: For the steppings affected, see the Summary Table of Changes.
S12 Processor issues inconsistent transaction size attributes for
locked operation
Problem: When the processor is in the Page Address Extension (PAE) mode and detects
the need to set the Access and/or Dirty bits in the page directory or page table
entries, the processor sends an 8-byte load lock onto the system bus. A
subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock
occurs. Correct data is provided since only the lower bytes change, however
external logic monitoring the data transfer may be expecting an 8-byte store
unlock.
Implication: This erratum affects no known commercially available chipsets.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S13 When the processor is in the system management mode (SMM),
Debug registers may be fully writeable
Problem: When in system management mode (SMM), the processor executes code and
stores data in the SMRAM space. When the processor is in this mode and
writes are made to DR6 and DR7, the processor should block writes to the
reserved bit locations. Due to this erratum, the processor may not block these
writes. This may result in invalid data in the reserved bit locations.
Implication: Reserved bit locations within DR6 and DR7 may become invalid.
Workaround:Software may perform a read/modify/write when writing to DR6 and DR7 to
ensure that the values in the reserved bits are maintained.
Status: For the steppings affected, see the Summary Table of Changes.