64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

24 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update
Errata
should be unaffected by the halted logical processor. Due to this erratum, the duty cycle is
incorrectly chosen to be the higher duty cycle of both logical processors.
Implication: Due to this erratum, higher duty cycle may be chosen when the on-demand clock modulation is
enabled on both logical processors.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U26 Memory aliasing of pages as uncacheable memory type and Write Back
(WB) may hang the system
Problem: When a page is being accessed as either UC or write combining (WC) and write back (WB), under
certain bus and memory timing conditions, the system may loop in a continual sequence of UC
fetch, implicit write back, and RFO retries.
Implication: This erratum has not been observed in any commercially available operating system or application.
The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as
being unsupported in the IA-32 Intel
®
Architecture Software Developer's Manual, Volume 3,
Section 10.12.4, Programming the PAT. However, if this erratum occurs the system may hang.
Workaround: The pages should not be mapped as either UC or WC and WB at the same time.
Status: For the steppings affected, see the Summary Table of Changes.
U27 Interactions between the Instruction Translation Lookaside Buffer (ITLB)
and the Instruction streaming buffer may cause unpredictable software
behavior
Problem: Complex interactions within the instruction fetch/decode unit may make it possible for the
processor to execute instructions from an internal streaming buffer containing stale or incorrect
information.
Implication: When this erratum occurs, an incorrect instruction stream may be executed resulting in
unpredictable software behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U28 Using STPCLK# and executing code from very slow memory could lead to a
system hang
Problem: The system may hang when the following conditions are met:
1. Periodic STPCLK# mechanism is enabled via the chipset.
2. HT Technology is enabled.
3. One logical processor is waiting for an event (i.e. hardware interrupt).
4. The other logical processor executes code from very slow memory such that every code fetch
is deferred long enough for the STPCLK# to be reasserted.
Implication: If this erratum occurs, the processor will go into and out of the sleep state without making forward
progress, since the logical processor will not be able to service any pending event. This erratum has
not been observed in any commercial platform running commercial software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.