Intel Xeon Processor MP Specification Update

Intel
®
Xeon
®
Processor MP Specification Update 17
Summary Tables of Changes
O53 XX
XX
No Fix Parity error in the L1 cache may cause the processor to hang
O54 XX
X
Fixed The TCK input in the test access port (TAP) is sensitive to low
clock edge rates and prone to noise coupling onto TCK's rising or
falling edges
O55 XXXXNo FixDisabling a local APIC disables both logical processor APICs on a
Hyper-Threading Technology enabled processor
O56 XXXXNo FixUsing STPCLK and executing code from very slow memory could
lead to a system hang
O57 X X Plan Fix Simultaneous cache line eviction from L2 and L3 caches may
result in the write back of stale data
O58 XXXXNo FixThe state of the resume flag (RF flag) in a task-state segment
(TSS) may be incorrect
O59 xNo FixChanges to CR3 register do not fence pending instruction page
O60 X X X X Plan Fix Simultaneous page-faults at similar page offsets on both logical
processors of an Hyper-Threading Technology enabled processor
may cause application failure
O61 X X X X No Fix A 16-bit address wrap resulting from a near branch (jump or call)
may cause an incorrect address to be reported to the #GP
exception handler
O62 X Fixed Incorrect PIROM L3 cache present value
O63 XXXXNo FixLocks and SMC detection may cause the processor to temporarily
hang
O64 XXXXNo FixIncorrect debug exception (#DB) may occur when a data
breakpoint is set on an FP instruction
O65 XXNo FixModified cache line eviction from L2 cache may result in write
back of stale data
O66 XXXXNo FixxAPIC may not report some illegal vector errors
O67 X X X X Plan Fix Incorrect duty cycle is chosen when On-Demand Clock
Modulation is enabled in a processor supporting Hyper-Threading
Technology
O68 X X X X Plan Fix Memory aliasing of pages as uncacheable memory type and write
back (WB) may hang the system
O69 X X Plan Fix A timing marginality in the Instruction Decoder unit may cause an
unpredictable application behavior and/or system hang
O70 XXXXNo FixMissing Stop Grant Acknowledge special bus cycle may cause a
system hang
O71 XXXXNo FixMachine check exceptions may not update Last-Exception Record
MSRs (LERs)
O72 XXXXNo FixStores to page tables may not be visible to page walks for
subsequent loads without serializing or invalidating the page table
entry
O73 X X Plan Fix A timing marginality in the Arithmetic Logic Unit (ALU) may cause
indeterminate behavior
O74 XXXXNo FixWith Trap Flag (TF) asserted, FP instruction that triggers an
unmasked FP exception may take single step trap before
retirement of instruction
O75 XXXXNo FixPDE/PTE loads and continuous locked updates to the same
cache line may cause a system livelock
Errata (Sheet 3 of 4)
No.
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Plans Errata