Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 9
13.5 CK408 Schematic Checklist ..............................................................................242
13.6 SSI Schematic Checklist ...................................................................................243
14 Layout Checklist..................................................................................................... 245
14.1 Processor Checklist...........................................................................................245
14.2 Processor Power Delivery Layout Checklist......................................................247
14.3 MCH Layout Checklist.......................................................................................251
14.4 Intel
®
ICH3-S Layout Checklist ........................................................................254
14.5 Intel
®
P64H2 Layout Checklist ..........................................................................258
14.6 SSI Layout Checklist .........................................................................................258
15 Schematics ...............................................................................................................259
Figures
1-1 Example Intel
®
E7500/E7501 Chipset-Based System Configuration.................26
2-1 Intel
®
Xeon™ Processor Quadrant Layout (Top View) ......................................28
2-2 Intel
®
E7500/E7501 Chipset MCH Quadrant Layout (Top View) ........................29
2-3 Intel
®
ICH3-S Quadrant Layout (Top View) ........................................................30
2-4 Intel
®
P64H2 Quadrant Layout (Top View) .........................................................31
3-1 8 Layer, 50 Ω Board with 5-Mil Traces................................................................33
3-2 Retention Mechanism Placement and Keep-Out Overview ................................35
3-3 Retention Mechanism Ground Ring ....................................................................36
3-4 Typical 2U Rack Optimized Board System Placement Example ........................37
3-5 Available Baseboard Mounting Holes Supported by the Chassis .......................38
3-6 Available Baseboard Mounting Holes Supported by the Chassis for the
Processor ............................................................................................................39
3-7 Baseboard Mounting Holes Used by Intel
®
E7501 Reference Board ................ 40
3-8 Typical Baseboard Maximum Height Restrictions...............................................41
3-9 EEB Case-2: 2-Dimensional End View of a Low Profile / High-Density
Server Application ...............................................................................................41
3-10 Standard I/O Cutout ............................................................................................ 42
4-1 System Clocking Diagram ...................................................................................47
4-2 Source Shunt Termination...................................................................................48
4-3 Clock Skew As Measured from Agent to Agent ..................................................50
4-4 Trace Spacing for HOST_CLK Clocks ................................................................ 50
4-5 Stuffing Options for CK408 and CK408B ............................................................ 51
4-6 Topology for CLK66 ............................................................................................52
4-7 Clock Skew Requirements ..................................................................................53
4-8 Example of Adding a Single Connector...............................................................54
4-9 Example of Adding Two Connectors and/or a Riser ...........................................54
4-10 Topology for CLK33_ICH3-S...............................................................................55
4-11 Topology for CLK33 to PCI Device Down ...........................................................56
4-12 Topology for CLK33 to PCI Slot ..........................................................................57
4-13 Topology for CLK14 ............................................................................................ 58
4-14 Topology for USB_CLK .......................................................................................59
4-15 Decoupling Capacitors Placement and Connectivity ..........................................60
5-1 Dual Processor System Bus Topology................................................................64
5-2 RESET# Topology...............................................................................................66