Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 85
Memory Interface Routing Guidelines
Certain combinations of DIMM types in 3-DIMM and 4-DIMM per channel systems have been
found to violate the JEDEC write ring back measurement specification. 1-DIMM and 2-DIMM per
channel systems do not violate the JEDEC write ring back specification. When combining double-
rank DIMMs (x4 or x8) with single-rank DIMMs (x4 or x8), if the first populated slot (closest to
the MCH) contains a single-ranked DIMM, the write ringback at that DIMM violates the JEDEC
DRAM specification. To reduce write ring back, populate single-ranked DIMMs furthest from the
MCH when a combination of single-ranked and double-ranked DIMMs is used.
To determine if a registered DDR DIMM is a single-bank DIMM or a double-bank DIMM, refer to
your Intel representative for more information.
Figure 6-3. Example of Proper Single and Dual Rank Mixing
Figure 6-4. Example of Incorrect Single and Dual Rank Mixing
MCH
Single Rank DIMM A3 Single Rank DIMM B3
Dual Rank DIMM A2 Dual Rank DIMM B2 Dual Rank DIMM A1 Dual Rank DIMM B1
MCH
Dual Rank DIMM A3 Dual Rank DIMM B3
Dual Rank DIMM A2
Dual Rank DIMM B2
Single Rank DIMM A1 Single Rank DIMM B1