Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 13
4-8 CLK14 Routing Guidelines ..................................................................................58
4-9 USBCLK Routing Guidelines...............................................................................59
5-1 System Bus Signal Groups .................................................................................63
5-2 System Bus Routing Summary ...........................................................................64
5-3 2X and 4X Signal Groups....................................................................................65
5-4 Source Synchronous Signals with the Associated Strobes.................................65
5-5 AGTL+ Common Clock I/O Signals.....................................................................66
5-6 BR[3:0]# Connection ........................................................................................... 67
5-7 Asynchronous GTL+ and Miscellaneous Signals ................................................68
5-8 Pin AE4 Signal Values Seen at mPGA604 Socket .............................................73
5-9 Functionality for SMBus and Thermal Diode Pins...............................................75
5-10 Thermal Sensor Devices .....................................................................................79
5-11 Alternative Method to Obtain Processor Information...........................................80
5-12 BSEL[1:0] Output ................................................................................................81
5-13 Functionality of SKTOCC# and VR Output .........................................................82
6-1 DDR Channel Signal Groups ..............................................................................83
6-2 Trace Width to impedance Requirements ...........................................................86
6-3 DQ/CB to DQS Mapping .....................................................................................87
6-4 Source Synchronous Signal Group Routing Guidelines......................................88
6-5 Command Clock Pair Routing Guidelines ...........................................................89
6-6 Source Clocked Signal Group Routing Guidelines..............................................91
6-7 Chip Select Routing Guidelines........................................................................... 92
6-8 Clock Enable Routing Guidelines........................................................................93
6-9 DC Biasing Ball Differences Between Intel
®
E7500 Chipset MCH and
Intel
®
E7501 Chipset MCH..................................................................................94
6-10 Receive Enable Routing Guidelines....................................................................95
6-11 DDRCOMP Routing Guidelines ..........................................................................96
6-12 DDRCVOL and DDRCVOH Routing Guidelines .................................................99
7-1 Hub Interface 2.0 Signal/Strobe Association..................................................... 104
7-2 Hub Interface 2.0 Signal Groups .......................................................................104
7-3 Hub Interface 2.0 Routing Parameters..............................................................104
7-4 Hub Interface 2.0 Reference Circuit Specifications...........................................107
7-5 Hub Interface 2.0 RCOMP Resistor Values ......................................................108
7-6 Hub Interface 1.5 Signal Groups .......................................................................109
7-7 Hub Interface 1.5 Routing Parameters..............................................................109
7-8 Hub Interface 1.5 Reference Circuit Specifications...........................................110
7-9 Hub Interface 1.5 RCOMP Resistor Values ......................................................111
8-1 PCI/PCI-X Frequencies .....................................................................................113
8-2 Simulated Timing Critical Signals......................................................................114
8-3 PCI/PCI-X Mode and Frequency Ordering........................................................114
8-4 Intel
®
P64H2 PCI/PCI-X Length Requirements ............................................... 115
8-5 Intel
®
P64H2 Hot-Plug Length Requirements ..................................................116
8-6 PCI-X Riser Card Length Requirements ...........................................................117
8-7 Device Down before PCI-X Riser Card Length Requirements.......................... 118
8-8 Device Down after PCI-X Riser Card Length Requirements.............................118
8-9 Device Down with Stub before PCI-X Riser Card Length Requirements ..........119
8-10 Two Devices Down Length Requirements ........................................................119
8-11 Hot-Plug Clock Routing Length Parameters ..................................................... 120
8-12 No Hot-Plug Clock Routing Length Parameters................................................120
8-13 Loop Clock Configuration Routing Length Parameters .....................................121