64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
August 2009 Specification Update
Order Number: 302402-024 17
—Intel
®
Xeon™ Processor with 800 MHz System Bus
35 XXXXXNo Fix
Data breakpoints on the high half of a floating-point
line split may not be captured
36 XXXXXNo Fix
Machine Check Exceptions may not update Last-
Exception Record MSRs (LERs)
37 XXXXXNo Fix
MOV CR3 performs incorrect reserved bit checking
when in PAE paging
38 XXXXXNo Fix
Stores to page tables may not be visible to pagewalks
for subsequent loads without serializing or
invalidating the page table entry
39 X Fixed
A split store memory access may miss
adatabreakpoint
40 X Fixed
EFLAGS.RF may be incorrectly set after an IRET
instruction
41 X Fixed
Writing the Echo TPR disable bit in
IA32_MISC_ENABLE may cause a #GP fault
42 X Fixed
Incorrect access controls to
MSR_LASTBRANCH_0_FROM_LIP MSR registers
43 XX Fixed Recursive page walks may cause a system hang
44 X Fixed
WRMSR to bit[0] of IA32_MISC_ENABLE register
changes only one logical processor on a Hyper-
Threading Technology enabled processor
45 XXXX Fixed
VERR/VERW instructions may cause #GP fault when
descriptor is in non-canonical space
46 X Fixed
INS or REP INS flows save an incorrect memory
address for SMI on processors supporting Intel®
Extended Memory 64 Technology (Intel® EM64T)
47 X Fixed
FXSAVE instruction may result in incorrect data on
processors supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
48 XX Fixed
The base of a null segment may be non-zero on a
processor supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
49 XX Fixed
Upper 32 bits of FS/GS with null base may not get
cleared in Virtual-8086 Mode on processors with
Intel® Extended Memory 64 Technology (Intel®
EM64T) Enabled
50 XXXXXNo Fix
Processor may fault when the upper 8 bytes of
segment selector is loaded from a far jump through a
call gate via the Local Descriptor Table
51 X Fixed
Compatibility mode STOS instructions may alter RSI
register results on a processor supporting Intel®
Extended Memory 64 Technology (Intel® EM64T)
52 X Fixed
LDT descriptor which crosses 16 bit boundary access
does not cause a #GP fault on a processor supporting
Intel® Extended Memory 64 Technology (Intel®
EM64T)
3.2 Errata (Sheet 3 of 6)
No.
D-0/
0F34
h
E-0/
0F41
h
G-1/
0F49
h
N-0/
0F43
h
R-0/
0F4A
h
Plans Errata