64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

64-bit Intel

Xeon

Processor MP with up to 8 MB L3 Cache Specification Update 23

Errata

U21 Incorrect debug exception (#DB) may occur when a data breakpoint is set

on an FP instruction

Problem: The default microcode FP event handler routine executes a series of loads to obtain data about the

FP instruction that is causing the FP event. If a data breakpoint is set on the instruction causing the

FP event, the load in the microcode routine will trigger the data breakpoint resulting in a debug

exception.

Implication: An incorrect debug exception (#DB) may occur if data breakpoint is placed on an FP instruction.

Intel has not observed this erratum with any commercially available software or system.

Workaround: None identified.

Status: For the steppings affected, see the Summary Table of Changes.

U22 xAPIC may not report some illegal vector errors

Problem: The local xAPIC has an error status register, which records all errors it detects. Bit 6 of this

message that it receives. When an illegal vector error is received on the same internal clock that the

error status register is being written due to a previous error, bit 6 does not get set and illegal vector

errors are not flagged.

Implication: The xAPIC may not report some Illegal Vector errors when they occur at approximately the same

time as other xAPIC errors. The other xAPIC errors will continue to be reported.

Workaround: None identified.

Status: For the steppings affected, see the Summary Table of Changes.

U23 Enabling no-eviction mode (NEM) may prevent the operation of the second

logical processor in a HT Technology enabled Boot Strap Processor (BSP)

Problem: In an HT Technology enabled system, when NEM is enabled by setting Bit 0 of MSR 080h

(IA32_BIOS_CACHE_AS_RAM), the second logical processor associated with the BSP may fail

to wake up from “Wait-for-SIPI” state.

Implication: In an HT Technology enabled system, the second logical processor associated with the BSP may

not respond to SIPI. The OS will continue to operate but with one less logical processor than

expected.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Table of Changes.

U24 Task Priority Register (TPR) updates during voltage transitions of power

management events may cause a system hang

Problem: Systems with Echo TPR Disable (R/W) bit (bit [23] of IA32_MISC_ENABLE register) set to '0'

(default), where xTPR messages are being transmitted on the system bus to the processor, may

experience a system hang during voltage transitions caused by the power management events.

Implication: This may cause a system hang during voltage transitions of power management events.

Workaround: It is possible for the BIOS to contain a workaround for this erratum. The BIOS workaround

disables the Echo TPR updates on affected steppings.

Status: For the steppings affected, see the Summary Table of Changes.

U25 Incorrect duty cycle is chosen when on-demand clock modulation is

enabled in a processor supporting HT Technology

Problem: When a processor supporting HT Technology enables on-demand clock modulation on both logical

processors, the processor is expected to select the lowest duty cycle of the two potentially different

values. When one logical processor enters the AUTOHALT state, the duty cycle implemented