64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update 13
Summary Table of Changes
J30 X X No Fix Machine check architecture error reporting and recovery may not work as expected
J31 X X No Fix Execution of IRET and INTn instructions may cause unexpected system behavior
J32 X X No Fix Data breakpoints on the high half of a floating-point line split may not be captured
J33 X X No Fix Machine check exceptions may not update Last-exception Record MSRs (LERs)
J34 X X No Fix MOV CR3 performs incorrect reserved bit checking when in PAE paging
J35 X X No Fix Stores to page tables may not be visible to pagewalks for subsequent loads without
serializing or invalidating the page table entry
J36 X X No Fix Recursive page walks may cause a system hang
J37 X X No Fix VERR/VERW instructions may cause #GP fault when descriptor is in non-canonical space
J38 X X No Fix The base of a null segment may be non-zero on a processor supporting Intel
®
Extended
Memory 64 Technology (Intel
®
EM64T)
J39 X X No Fix Upper 32 Bits of FS/GS with null base may not get cleared in Virtual-8086 Mode on
processors with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) Enabled
J40 X X No Fix Processor may fault when the upper 8 bytes of segment selector is loaded from a far jump
through a call gate via the local descriptor table
J41 X X No Fix Loading a stack segment with a selector that references a non-canonical address can lead
to a #SS fault on a processor supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
J42 X X No Fix FXRSTOR may not restore non-canonical effective addresses on processors with Intel*sup
J43 X X No Fix A push of ESP that faults may zero the upper 32 bits of RSP
J44 X X No Fix Enhanced halt state (C1E) voltage transition may affect a system’s power management in a
Hyper-Threading Technology enabled processor
J45 X X No Fix Enhanced halt state (C1E) may not be entered in a Hyper-Threading Technology enabled
processor
J46 X X No Fix When the execute disable bit function is enabled a page fault in a mispredicted branch may
result in a page fault exception
J47 X X No Fix Execute disable bit set with AD assist may cause livelock
J48 X X No Fix The execute disable bit fault may be reported before other types of page fault when both
occur
J49 X X No Fix Writes to IA32_MISC_ENABLE may not update flags for both logical processors
J50 X X No Fix Execute disable bit set with CR4.PAE may cause livelock
J51 X X No Fix Checking of page table base address may not match the address bit width supported by the
platform
J52 X X No Fix IA32_MCi_STATUS MSR may improperly indicate that additional MCA information may
have been captured
J53 X X No Fix With Trap Flag (TF) asserted, FP instruction that triggers an unmasked FP exception may
take single step trap before retirement of instruction
J54 X X No Fix PDE/PTE loads and continuous locked updates to the same cache line may cause a
system livelock
J55 X X No Fix Branch Trace Store (BTS) and Precise Event Based Sampling (PEBS) may update memory
outside the BTS/PEBS buffer
J56 X X No Fix L-bit of the CS and LMA bit of the IA32_EFER register may have an erroneous value for
one instruction following a mode transition in a Hyper-Threading Technology enabled
processor supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Errata (Sheet 2 of 3)
No.
A-0/
0F41h
B-0/
0F49H
Plans Errata