ITP700 Debug Port Design Guide

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4 ITP700 Debug Port Design Guide
7.1.1
ITP Clock Routing for Intel
®
Pentium
®
4 Processor .............................. 61
7.1.1.1 Option A) Using the CK408 Clock Generator ...................... 61
7.1.1.2 Option B) Using the ITPCLKOUT[1:0] Pins: (For B0 Silicon
or Greater) ........................................................................... 62
8 Intel
®
Itanium
®
2 Processor System Implementation Guidelines ...................................... 65
8.1 ITP DC and AC Electrical Specifications for Intel
®
Itanium
®
2 Processor
Systems ................................................................................................................ 65
8.1.1 DC Electrical Specifications .................................................................. 65
8.1.2 AC Electrical Specifications .................................................................. 69
8.2 ITP Signal Layout Guidelines ............................................................................... 70
8.2.1 System Signal Layout Guidelines.......................................................... 71
8.2.2 JTAG Signal Layout Guidelines ............................................................ 71
8.2.3 BPM Connectivity for I/O Domain Debug Ports .................................... 72
8.3 Intel
®
Itanium
®
2 Processor Routing Guidelines................................................... 73
9 Intel
®
E8870 Chipset System Implementation Guidelines................................................. 75
9.1 The I/O Domain Debug Port Guidelines ............................................................... 75
9.2 The Miscellaneous Debug Port Guidelines .......................................................... 76
10 Appendix A – Alternate Bypass Methods .......................................................................... 77
11 Appendix B – Buffering TCK ............................................................................................. 81
12 Appendix C – Recovering a Single-Ended BCLK.............................................................. 83
13 Appendix D – Arbitration of the Scan Chain With a Local TAP Master............................. 85
14 Appendix E – Designer’s Checklist for Schematic and Layout Reviews........................... 87
15 Appendix F – ITP700 DPA Spice Models.......................................................................... 91