Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

R
D
C
B
B
D
C
1
12345678
2345678
A
A
LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
74HCT4052
GND
Z1
Z2
VEE
VCC
S0
S1
EN_N
Y1_3
Y1_2
Y1_1
Y1_0
Y2_3
Y2_2
Y2_1
Y2_0
+VSBY5_0
+V3_3
+V3_3
+V3_3
+VSBY5_0
+VSBY5_0
+VSBY3_3
SN74CBTD3306
2A
2B
2OE_N
VCC
GND
1B
1A
1OE_N
SN74CBTD3306
2A
2B
2OE_N
VCC
GND
1B
1A
1OE_N
SN74CBTD3306
2A
2B
2OE_N
VCC
GND
1B
1A
1OE_N
SN74CBTD3306
2A
2B
2OE_N
VCC
GND
1B
1A
1OE_N
+VSBY5_0;14
GND;7
0 0
SMBus Partition
SEL1 SEL0
0 1
01
1 1
Bus 0
Bus 1
Bus 2
Bus 3 (default)
SMBus Mux
SMBus Isolation and Voltage Translation
71 85
C1692
0.1UF
R780
4.7K 4.7K
R779
R771
3.3K 3.3K
R772
1 2
U81
2
3
1
JP14
1
3
2
JP15
2
3
1
JP16
1
3
2
JP17
5
6
7
8
4
3
2
1
U24
5
6
7
8
4
3
2
1
U23
C1696
0.1UF
0.1UF
C1695
C1694
0.1UF
0.1UF
C1693
ICH3_SLP_S5_N
63,82
5
6
7
8
4
3
2
1
U13
5
6
7
8
4
3
2
1
U12
I2C_BUS3_DAT
16,17,18,21,22,23,71,80
I2C_BUS3_CLK
16,17,18,21,22,23,71,80
I2C_BUS2_DAT
4,5,6,7,11,37,71
I2C_BUS2_CLK
4,5,6,7,11,37,71
I2C_BUS1_DAT
27,31,42,43,60,71
I2C_BUS1_CLK
27,31,42,43,60,71
ICH3_SMBUS_SEL062
ICH3_SMBUS_SEL1
62
I2C_BUS0_EN_N
I2C_BUS0_DAT_3V71
R768
4.7K
R777
1K
4.7K
R775 R769
4.7K 4.7K
R770
I2C_ISOLATE
I2C_BUS1_DAT_MUX
71
I2C_BUS1_CLK_MUX 71
I2C_BUS1_DAT_MUX 71
I2C_BUS3_DAT_MUX 71
I2C_BUS2_DAT_MUX 71
I2C_BUS0_DAT_3V 71
I2C_BUS0_CLK_3V
71
I2C_BUS0_CLK_3V 71
71,82
I2C_BUS0_CLK
71,82
I2C_BUS0_DAT
27,31,42,43,60,71
I2C_BUS1_DAT
27,31,42,43,60,71
I2C_BUS1_CLK
I2C_BUS2_CLK_MUX 71
I2C_BUS3_CLK_MUX 71
I2C_BUS2_DAT_MUX
71
I2C_BUS3_DAT_MUX
71
I2C_BUS2_CLK_MUX
71
I2C_BUS3_CLK_MUX
71
I2C_BUS0_CLK
71,82
I2C_BUS0_DAT
71,82
R773
4.7K 4.7K
R774R776
4.7K
100
R778
16,17,18,21,22,23,71,80
I2C_BUS3_CLK
16,17,18,21,22,23,71,80
I2C_BUS3_DAT
4,5,6,7,11,37,71
I2C_BUS2_DAT
4,5,6,7,11,37,71
I2C_BUS2_CLK
I2C_BUS1_CLK_MUX 71
ICH3_SMBDATA62
ICH3_SMBCLK
62
8
13
3
7
16
10
9
6
11
15
14
12
4
2
5
1
U72
1.0INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD
11/18/02