64-bit Intel Xeon Processor MP with up to 8MB L3 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update 41
Specification Clarifications
• Time-stamp counter — Some processor models permit clock cycles to be measured when the
physical processor is not in deep sleep (by using the time-stamp counter and the RDTSC
instruction). Note that such ticks cannot be measured on a per-logical-processor basis. See
Section 10.8 for detail on processor capabilities.
The first two methods use performance counters and can be set up to cause an interrupt upon
overflow (for sampling). They may also be useful where it is easier for a tool to read a performance
counter than to use a time stamp counter (the timestamp counter is accessed using the RDTSC
instruction).
For applications with a significant amount of I/O, there are two ratios of interest:
• Non-halted CPI — Non-halted clockticks/instructions retired measures the CPI for phases
where the CPU was being used. This ratio can be measured on a logical-processor basis when
Hyper-Threading Technology is enabled.
• Nominal CPI — Time-stamp counter ticks/instructions retired measures the CPI over the
duration of a program, including those periods when the machine halts while waiting for I/O.
15.10.9.3 Incrementing the Time-Stamp Counter
The time-stamp counter increments when the clock signal on the system bus is active and when the
sleep pin is not asserted. The counter value can be read with the RDTSC instruction.
The time-stamp counter and the non-sleep clockticks count may not agree in all cases and for all
processors. See Section 10.8 for more information on counter operation.