Intel Xeon Processor Multiprocessor Platform Design Guide

3
Contents
1 Introduction ................................................................................................................ 11
1.1 Related Documentation.......................................................................................11
1.2 Conventions and Terminology.............................................................................13
2 System Overview......................................................................................................17
2.1 The Intel
®
Xeon™ Processor MP and the Intel
®
Xeon™ Processor MP
with up to 2-MB L3 Cache on the 0.13 Micron Process ......................................17
2.2 Bandwidth Summary ...........................................................................................18
3 Processor Quadrant Layout ................................................................................19
4 Platform Stack-Up and Placement Overview................................................21
4.1 Platform Component Placement .........................................................................21
4.2 4-Way System Stack-Up .....................................................................................22
4.2.1 Design Recommendations .....................................................................22
4.2.2 Design Considerations ...........................................................................23
5 Clock Routing Guidelines.....................................................................................25
5.1 System Bus Clocking Guidelines ........................................................................25
5.1.1 Routing Guidelines for BCLK[1:0] ..........................................................25
6 System Bus Routing ...............................................................................................31
6.1 Return Path .........................................................................................................32
6.2 Serpentine Routing..............................................................................................33
6.3 System Bus Decoupling Requirements...............................................................33
6.3.1 Processor I/O Decoupling Requirements ............................................... 34
6.3.2 Chipset System Bus I/O Decoupling Recommendations .......................35
6.4 Routing Guidelines for a 4-Way System ............................................................. 35
6.4.1 Topology and Routing ............................................................................37
6.4.1.1 Design Recommendations ........................................................37
6.4.1.2 4X Group (DSTBP [3:0]#, DSTBN [3:0]#, D [63:0]#,
DBI [3:0]#) .................................................................................38
6.4.1.3 2X Address Group (ADSTB [2:0]#, A [35:3]#, REQ [4:0]#) ....... 41
6.4.1.4 Common Clock.......................................................................... 41
6.4.1.5 Wired-OR ..................................................................................41
6.4.1.6 Design Considerations .............................................................. 42
6.4.2 Routing Guidelines for Asynchronous GTL+ and Other Signals ............43
6.4.2.1 Topology 1: Asynchronous GTL+ Signals Driven by the
Processors; FERR#, IERR#, PROCHOT# and
THERMTRIP# ...........................................................................44
6.4.2.2 Topology 2: Asynchronous GTL+ Signals Driven by the
Chipset; A20M#, IGNNE#, INIT#, LINT[1:0], PWRGOOD,
SLP#, SMI#, and STPCLK# ......................................................46
6.4.2.3 Topology 3: VID[4:0]..................................................................46
6.4.2.4 Topology 4: SMBus Signals ......................................................46
6.4.2.5 Topology 5: BR[3:0]# Signals....................................................47
6.4.2.6 Topology 6: COMP[1:0] Signals ................................................ 48
6.4.2.7 Topology 7: ODTEN Signal .......................................................48
6.4.2.8 Topology 8: TESTHI[6:0] Signals ..............................................48