Intel Xeon Processor Multiprocessor Platform Design Guide

15
Introduction
Convention/
Terminology
Definition
SSO
Simultaneous Switching Output (SSO) Effects refers to the difference in electrical timing
parameters and degradation in signal quality caused by multiple signal outputs
simultaneously switching voltage levels (e.g., high-to-low) in the opposite direction from a
single signal (e.g., low-to-high) or in the same direction (e.g., high-to-low). These are
respectively called odd-mode switching and even-mode switching. This simultaneous
switching of multiple outputs creates higher current swings that may cause additional
propagation delay (or “push-out”), or a decrease in propagation delay (or “pull-in”). These
SSO effects may impact the setup and/or hold times and are not always taken into account
by simulations. System timing budgets should include margin for SSO effects.
Stub The branch from the bus trunk terminating at the pad of an agent.
System Bus Used in this document to refer to the scalable system bus.
Test Load Intel uses a 50 Ω test load for specifying its components.
Trunk
The main connection, excluding interconnect branches, from one end agent pad to the
other end agent pad.
Undershoot Minimum voltage observed for a signal to extend below V
SS
at the device pad.
V
CC_CPU
V
CC_CPU
is the processor power for both the core and the system bus I/O.
Victim
A network that receives a coupled crosstalk signal from another network is called the victim
network.
GTLREF
Guardband
A guardband defined above and below GTLREF to provide a more realistic model
accounting for noise such as VTT
and GTLREF noise.
VRM 9.1
“VRM 9.1” refers to the Voltage Regulator Module for the processor. It is a DC-DC
converter module that supplies the required voltage and current to a single processor.
Table 1-2. Platform Conventions and Terminology (Sheet 3 of 3)