Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

System Bus Routing Guidelines
78 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
5.5.2.2 Firmware Selection of SMBus Thermal Devices
This section describes a firmware method for supporting either the Intel Xeon processor with
512-KB L2 cache or the Intel Xeon processor with 533 MHz system bus. This method is based on
the thermal sensor implementation illustrated in Figure 5-12. The board designer can route each
processor’s SMB_PRT to an ICH3-S GPIO pin, Baseboard Management Controller GPIO pin, or
any other ASIC or microcontroller. Likewise, any Baseboard Management Controller,
microcontroller, or ASIC can also be used as a thermal sensor. Firmware can detect whether the
signal is low or high to determine which device to address the processor temperature. If the signal
is high, then an Intel Xeon processor with 512-KB L2 cache is installed and the SMBus controller
can access the processor SMBus target. If an Intel Xeon processor with 533 MHz system bus is
installed, SMB_PRT is low and the SMBus controller knows to access the other device which
contains a thermal sensor. Both the processor and the controller or ASIC must have different
addresses so that they can be differentiated on the SMBus. The advantage of this method over the
hardware option discussed in the previous section is that no mux device is required.
Figure 5-12. Circuit Implementation for Firmware-Based SMBus Selection
D-
D+
Controller
or ASIC
STBY#
SCLK
SDATA
ALRT#
SM_CLK
SM_DAT
SM_ALERT#
Onboard
Signals
Y28
Y27
Processor
AC28
AC29
AD28
THERMDA
THERMDC
SM_CLK
SM_DAT
SM_ALERT#
AA28
Y29
SM_TS1_A0
SM_TS1_A1
SMB_PRT
Use any Combination of
resistors for addresses.
AE4
SM_VCC
SMB_PRT
SM_VCC
Processor and Controller use
different addresses