Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 151
I/O Controller Hub 3 (Intel
®
ICH3-S)
9.5.3 High Power/Low Power Mixed Architecture
This design allows for current isolation of high and low current devices while also allowing
SMBus devices to communicate while in S5. VCC_SUSPEND leakage is minimized by keeping
non-essential devices on the core supply. This is accomplished by the use of a “FET” to isolate the
devices powered by the core and suspend supplies. See Figure 9-8.
Added Considerations for Mixed Architecture:
• The bus switch must be powered by VCC_SUSPEND.
• Devices that are powered by the VCC_SUSPEND well must not drive into other devices that
are powered off. This is accomplished with the “bus switch”.
• The bus bridge can be a device like the Phillips PCA9515.
Figure 9-8. High Power/Low Power Mixed VCC_SUSPEND/ VCC_CORE Architecture
Intel
®
ICH3-S
High
Current
Low
Current
VccSusVccSus3_3
Vcc
SMBus
Devices running in S5
-
Non S5 devices
Vcc VccSus VccSus3_3
SMBus
Vcc
SMBus
Devices running in S5
-
Non S5 devices
Vcc
Bus Bridge
Buffered Power Good
Signal From Power Supply
Buffered Power Good
Signal From Power Supply