Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 99
Memory Interface Routing Guidelines
6.7.4 DDRCVO
The MCH uses a compensation signal to adjust buffer characteristics and output voltage swing over
temperature, process, and voltage skew. Calibration is done periodically by sampling the
DDRCVO_x pins on the MCH. Place the voltage divider network (Figure 6-17) within 1 inch of
the MCH. When an E7501 chipset MCH is used on a compatible board, all of the components on
the DDRCVOL circuit do not need to be stuffed, as shown in Figure 6-17. Also, a compatible
footprint should be used between the resistor and the capacitor stuffing options. A 0603 resistor is
sufficient for power dissipation. For an E7501 chipset MCH only design, omit the entire upper
circuit in Figure 6-17 from the board. Also, on E7501 chipset MCH only designs, the empty pull-
down stuffing option to DDR VTERM is not needed.
NOTE: ‘x’ indicates channel A or B.
Table 6-12. DDRCVOL and DDRCVOH Routing Guidelines
Parameter Intel
®
E7500 Chipset MCH Intel
®
E7501 Chipset MCH
Topology Resistor Divider Resistor Divider
Nominal Trace Width 15 mil 15 mil
Nominal Trace Spacing 20 mil 20 mil
Trace Length - MCH to Divider < 1.0” < 1.0”
Figure 6-17. DDRCVOL, DDRCVOH, and DDRCVO Network
Intel
®
E7500
chipset MCH
or
Intel
®
E7501
chipset MCH
E7500: DDRCVOH_x
E7501:DDRCVO_x
DDR VDD
(2.5 V)
DDR VTERM
(
1.25 V
)
< 1"
E7500: 13 kΩ ± 1%
E7501: 49.9 Ω ± 1%
E7500:
7 kΩ± 1%
E7501:
no pop
E7500:
0.1 µF
E7501:
49.9 Ω ± 1%
Use 0603
Footprint
DDR VTERM
(1.25 V)
< 1"
13 kΩ ± 1%
7 kΩ ± 1%
0.01 µF0.1 µF
E7500: DDRCVOL_x
E7501:No Connect
Do Not Stuff when
E7501 is used!
E7500:
0.01 µF
E7501:
1 nF